linux/arch/ia64/mm
Chen, Kenneth W 00b65985fb [IA64] relax per-cpu TLB requirement to DTC
Instead of pinning per-cpu TLB into a DTR, use DTC.  This will free up
one TLB entry for application, or even kernel if access pattern to
per-cpu data area has high temporal locality.

Since per-cpu is mapped at the top of region 7 address, we just need to
add special case in alt_dtlb_miss.  The physical address of per-cpu data
is already conveniently stored in IA64_KR(PER_CPU_DATA).  Latency for
alt_dtlb_miss is not affected as we can hide all the latency.  It was
measured that alt_dtlb_miss handler has 23 cycles latency before and
after the patch.

The performance effect is massive for applications that put lots of tlb
pressure on CPU.  Workload environment like database online transaction
processing or application uses tera-byte of memory would benefit the most.
Measurement with industry standard database benchmark shown an upward
of 1.6% gain.  While smaller workloads like cpu, java also showing small
improvement.

Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2007-02-06 15:04:48 -08:00
..
contig.c [IA64] fix arch/ia64/mm/contig.c:235: warning: unused variable `nid' 2006-12-12 11:18:55 -08:00
discontig.c [PATCH] mm: use symbolic names instead of indices for zone initialisation 2006-10-11 11:14:14 -07:00
extable.c Remove obsolete #include <linux/config.h> 2006-06-30 19:25:36 +02:00
fault.c [PATCH] pidspace: is_init() 2006-09-29 09:18:12 -07:00
hugetlbpage.c [PATCH] shared page table for hugetlb page 2006-12-07 08:39:21 -08:00
init.c [IA64] relax per-cpu TLB requirement to DTC 2007-02-06 15:04:48 -08:00
ioremap.c [IA64] sparse cleanups 2006-08-02 16:03:44 -07:00
Makefile [PATCH] ia64: ioremap: check EFI for valid memory attributes 2006-03-26 08:56:54 -08:00
numa.c [PATCH] hot-add-mem x86_64: memory_add_physaddr_to_nid node fixup 2006-10-01 00:39:18 -07:00
tlb.c Remove obsolete #include <linux/config.h> 2006-06-30 19:25:36 +02:00