3070033a16
More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Chris Dearman
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
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/*
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* CPU feature overrides for MIPS boards
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*/
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#ifdef CONFIG_CPU_MIPS32
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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/* #define cpu_has_fpu ? */
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/* #define cpu_has_32fpr ? */
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#define cpu_has_counter 1
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/* #define cpu_has_watch ? */
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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/* #define cpu_has_cache_cdex_p ? */
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/* #define cpu_has_cache_cdex_s ? */
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/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
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#ifdef CONFIG_CPU_HAS_LLSC
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#define cpu_has_llsc 1
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#else
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#define cpu_has_llsc 0
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#endif
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/* #define cpu_has_vtag_icache ? */
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/* #define cpu_has_dc_aliases ? */
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/* #define cpu_has_ic_fills_f_dc ? */
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#define cpu_has_nofpuex 0
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/* #define cpu_has_64bits ? */
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/* #define cpu_has_64bit_zero_reg ? */
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/* #define cpu_has_inclusive_pcaches ? */
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#define cpu_icache_snoops_remote_store 1
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#endif
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#ifdef CONFIG_CPU_MIPS64
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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/* #define cpu_has_fpu ? */
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/* #define cpu_has_32fpr ? */
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#define cpu_has_counter 1
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/* #define cpu_has_watch ? */
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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/* #define cpu_has_cache_cdex_p ? */
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/* #define cpu_has_cache_cdex_s ? */
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/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
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#define cpu_has_llsc 1
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/* #define cpu_has_vtag_icache ? */
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/* #define cpu_has_dc_aliases ? */
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/* #define cpu_has_ic_fills_f_dc ? */
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#define cpu_has_nofpuex 0
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/* #define cpu_has_64bits ? */
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/* #define cpu_has_64bit_zero_reg ? */
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/* #define cpu_has_inclusive_pcaches ? */
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#define cpu_icache_snoops_remote_store 1
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#endif
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#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
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