forked from Minki/linux
ba3579e6e4
The implementation is based on the 32-bit implementation of the aria. Also, aria-avx process steps are the similar to the camellia-avx. 1. Byteslice(16way) 2. Add-round-key. 3. Sbox 4. Diffusion layer. Except for s-box, all steps are the same as the aria-generic implementation. s-box step is very similar to camellia and sm4 implementation. There are 2 implementations for s-box step. One is to use AES-NI and affine transformation, which is the same as Camellia, sm4, and others. Another is to use GFNI. GFNI implementation is faster than AES-NI implementation. So, it uses GFNI implementation if the running CPU supports GFNI. There are 4 s-boxes in the ARIA and the 2 s-boxes are the same as AES's s-boxes. To calculate the first sbox, it just uses the aesenclast and then inverts shift_row. No more process is needed for this job because the first s-box is the same as the AES encryption s-box. To calculate the second sbox(invert of s1), it just uses the aesdeclast and then inverts shift_row. No more process is needed for this job because the second s-box is the same as the AES decryption s-box. To calculate the third s-box, it uses the aesenclast, then affine transformation, which is combined AES inverse affine and ARIA S2. To calculate the last s-box, it uses the aesdeclast, then affine transformation, which is combined X2 and AES forward affine. The optimized third and last s-box logic and GFNI s-box logic are implemented by Jussi Kivilinna. The aria-generic implementation is based on a 32-bit implementation, not an 8-bit implementation. the aria-avx Diffusion Layer implementation is based on aria-generic implementation because 8-bit implementation is not fit for parallel implementation but 32-bit is enough to fit for this. Signed-off-by: Taehee Yoo <ap420073@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
214 lines
6.1 KiB
C
214 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Glue Code for the AVX/AES-NI/GFNI assembler implementation of the ARIA Cipher
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*
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* Copyright (c) 2022 Taehee Yoo <ap420073@gmail.com>
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*/
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#include <crypto/algapi.h>
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#include <crypto/internal/simd.h>
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#include <crypto/aria.h>
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#include <linux/crypto.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include "ecb_cbc_helpers.h"
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#include "aria-avx.h"
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asmlinkage void aria_aesni_avx_encrypt_16way(const void *ctx, u8 *dst,
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const u8 *src);
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asmlinkage void aria_aesni_avx_decrypt_16way(const void *ctx, u8 *dst,
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const u8 *src);
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asmlinkage void aria_aesni_avx_ctr_crypt_16way(const void *ctx, u8 *dst,
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const u8 *src,
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u8 *keystream, u8 *iv);
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asmlinkage void aria_aesni_avx_gfni_encrypt_16way(const void *ctx, u8 *dst,
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const u8 *src);
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asmlinkage void aria_aesni_avx_gfni_decrypt_16way(const void *ctx, u8 *dst,
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const u8 *src);
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asmlinkage void aria_aesni_avx_gfni_ctr_crypt_16way(const void *ctx, u8 *dst,
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const u8 *src,
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u8 *keystream, u8 *iv);
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static struct aria_avx_ops aria_ops;
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static int ecb_do_encrypt(struct skcipher_request *req, const u32 *rkey)
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{
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ECB_WALK_START(req, ARIA_BLOCK_SIZE, ARIA_AESNI_PARALLEL_BLOCKS);
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ECB_BLOCK(ARIA_AESNI_PARALLEL_BLOCKS, aria_ops.aria_encrypt_16way);
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ECB_BLOCK(1, aria_encrypt);
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ECB_WALK_END();
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}
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static int ecb_do_decrypt(struct skcipher_request *req, const u32 *rkey)
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{
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ECB_WALK_START(req, ARIA_BLOCK_SIZE, ARIA_AESNI_PARALLEL_BLOCKS);
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ECB_BLOCK(ARIA_AESNI_PARALLEL_BLOCKS, aria_ops.aria_decrypt_16way);
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ECB_BLOCK(1, aria_decrypt);
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ECB_WALK_END();
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}
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static int aria_avx_ecb_encrypt(struct skcipher_request *req)
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{
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct aria_ctx *ctx = crypto_skcipher_ctx(tfm);
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return ecb_do_encrypt(req, ctx->enc_key[0]);
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}
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static int aria_avx_ecb_decrypt(struct skcipher_request *req)
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{
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct aria_ctx *ctx = crypto_skcipher_ctx(tfm);
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return ecb_do_decrypt(req, ctx->dec_key[0]);
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}
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static int aria_avx_set_key(struct crypto_skcipher *tfm, const u8 *key,
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unsigned int keylen)
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{
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return aria_set_key(&tfm->base, key, keylen);
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}
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static int aria_avx_ctr_encrypt(struct skcipher_request *req)
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{
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct aria_ctx *ctx = crypto_skcipher_ctx(tfm);
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struct skcipher_walk walk;
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unsigned int nbytes;
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int err;
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err = skcipher_walk_virt(&walk, req, false);
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while ((nbytes = walk.nbytes) > 0) {
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const u8 *src = walk.src.virt.addr;
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u8 *dst = walk.dst.virt.addr;
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while (nbytes >= ARIA_AESNI_PARALLEL_BLOCK_SIZE) {
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u8 keystream[ARIA_AESNI_PARALLEL_BLOCK_SIZE];
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kernel_fpu_begin();
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aria_ops.aria_ctr_crypt_16way(ctx, dst, src, keystream,
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walk.iv);
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kernel_fpu_end();
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dst += ARIA_AESNI_PARALLEL_BLOCK_SIZE;
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src += ARIA_AESNI_PARALLEL_BLOCK_SIZE;
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nbytes -= ARIA_AESNI_PARALLEL_BLOCK_SIZE;
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}
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while (nbytes >= ARIA_BLOCK_SIZE) {
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u8 keystream[ARIA_BLOCK_SIZE];
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memcpy(keystream, walk.iv, ARIA_BLOCK_SIZE);
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crypto_inc(walk.iv, ARIA_BLOCK_SIZE);
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aria_encrypt(ctx, keystream, keystream);
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crypto_xor_cpy(dst, src, keystream, ARIA_BLOCK_SIZE);
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dst += ARIA_BLOCK_SIZE;
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src += ARIA_BLOCK_SIZE;
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nbytes -= ARIA_BLOCK_SIZE;
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}
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if (walk.nbytes == walk.total && nbytes > 0) {
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u8 keystream[ARIA_BLOCK_SIZE];
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memcpy(keystream, walk.iv, ARIA_BLOCK_SIZE);
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crypto_inc(walk.iv, ARIA_BLOCK_SIZE);
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aria_encrypt(ctx, keystream, keystream);
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crypto_xor_cpy(dst, src, keystream, nbytes);
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dst += nbytes;
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src += nbytes;
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nbytes = 0;
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}
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err = skcipher_walk_done(&walk, nbytes);
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}
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return err;
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}
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static struct skcipher_alg aria_algs[] = {
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{
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.base.cra_name = "__ecb(aria)",
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.base.cra_driver_name = "__ecb-aria-avx",
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.base.cra_priority = 400,
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.base.cra_flags = CRYPTO_ALG_INTERNAL,
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.base.cra_blocksize = ARIA_BLOCK_SIZE,
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.base.cra_ctxsize = sizeof(struct aria_ctx),
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.base.cra_module = THIS_MODULE,
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.min_keysize = ARIA_MIN_KEY_SIZE,
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.max_keysize = ARIA_MAX_KEY_SIZE,
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.setkey = aria_avx_set_key,
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.encrypt = aria_avx_ecb_encrypt,
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.decrypt = aria_avx_ecb_decrypt,
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}, {
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.base.cra_name = "__ctr(aria)",
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.base.cra_driver_name = "__ctr-aria-avx",
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.base.cra_priority = 400,
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.base.cra_flags = CRYPTO_ALG_INTERNAL,
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.base.cra_blocksize = 1,
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.base.cra_ctxsize = sizeof(struct aria_ctx),
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.base.cra_module = THIS_MODULE,
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.min_keysize = ARIA_MIN_KEY_SIZE,
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.max_keysize = ARIA_MAX_KEY_SIZE,
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.ivsize = ARIA_BLOCK_SIZE,
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.chunksize = ARIA_BLOCK_SIZE,
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.walksize = 16 * ARIA_BLOCK_SIZE,
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.setkey = aria_avx_set_key,
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.encrypt = aria_avx_ctr_encrypt,
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.decrypt = aria_avx_ctr_encrypt,
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}
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};
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static struct simd_skcipher_alg *aria_simd_algs[ARRAY_SIZE(aria_algs)];
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static int __init aria_avx_init(void)
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{
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const char *feature_name;
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if (!boot_cpu_has(X86_FEATURE_AVX) ||
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!boot_cpu_has(X86_FEATURE_AES) ||
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!boot_cpu_has(X86_FEATURE_OSXSAVE)) {
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pr_info("AVX or AES-NI instructions are not detected.\n");
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return -ENODEV;
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}
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if (!cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM,
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&feature_name)) {
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pr_info("CPU feature '%s' is not supported.\n", feature_name);
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return -ENODEV;
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}
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if (boot_cpu_has(X86_FEATURE_GFNI)) {
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aria_ops.aria_encrypt_16way = aria_aesni_avx_gfni_encrypt_16way;
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aria_ops.aria_decrypt_16way = aria_aesni_avx_gfni_decrypt_16way;
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aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_gfni_ctr_crypt_16way;
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} else {
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aria_ops.aria_encrypt_16way = aria_aesni_avx_encrypt_16way;
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aria_ops.aria_decrypt_16way = aria_aesni_avx_decrypt_16way;
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aria_ops.aria_ctr_crypt_16way = aria_aesni_avx_ctr_crypt_16way;
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}
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return simd_register_skciphers_compat(aria_algs,
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ARRAY_SIZE(aria_algs),
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aria_simd_algs);
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}
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static void __exit aria_avx_exit(void)
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{
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simd_unregister_skciphers(aria_algs, ARRAY_SIZE(aria_algs),
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aria_simd_algs);
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}
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module_init(aria_avx_init);
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module_exit(aria_avx_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Taehee Yoo <ap420073@gmail.com>");
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MODULE_DESCRIPTION("ARIA Cipher Algorithm, AVX/AES-NI/GFNI optimized");
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MODULE_ALIAS_CRYPTO("aria");
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MODULE_ALIAS_CRYPTO("aria-aesni-avx");
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