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5724 Commits

Author SHA1 Message Date
Geert Uytterhoeven
4e1c5433cc pinctrl: renesas: r8a7779: Share MMC pin group data 
Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8.

This reduces kernel size by 80 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3484b3cd6b4ca19788fafc01f5ead4e067275e8d.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
e56ca224bd pinctrl: renesas: r8a7778: Share MMC pin group data 
Pin groups mmc_data[14] are subsets of mmc_data8.

This reduces kernel size by 40 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d3bf7dfda2952a0265171f82024931d490d9178a.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
b24cf384f9 pinctrl: renesas: r8a77470: Share MMC pin group data 
Pin groups mmc_data[14] and sdhi1_data[14] are subsets of mmc_data8.
Pin group sdhi1_ctrl can be an alias for mmc_ctrl.

This reduces kernel size by 96 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e3d19e19f7666dbcefeec351a5096a86348404ae.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
477001e542 pinctrl: renesas: r8a7740: Share MMC pin group data 
Pin groups mmc0_data[14]_[01] are subsets of mmc0_data8_[01].

This reduces kernel size by 80 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4b15d28bb8ac24417be83b1defe0bbb908abc1e6.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
d49f3be808 pinctrl: renesas: r8a73a4: Share MMC pin group data 
Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8.

This reduces kernel size by 80 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ad30961d71631577c2bdbf8dfa4874c9585caba9.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
3c52288bf0 pinctrl: renesas: sh73a0: Share LCD pin group data 
Pin groups lcd{,2}_data{8,9,12,16,18} are subsets of lcd{,2}_data24.

This reduces kernel size by 1008 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/32561ca31b590424f494351a737473200102bf8c.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
6558407e75 pinctrl: renesas: r8a7740: Share LCD pin group data 
Pin groups lcd0_data{8,9,12,16,18} are subsets of lcd0_data24_0.
Pin groups lcd1_data{8,9,12,16,18} are subsets of lcd1_data24.

This reduces kernel size by 1008 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2018113779b3084c4175b04bb32acf2de0557a37.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
12e9231ecc pinctrl: renesas: sh73a0: Share KEYIN pin group data 
Pin groups keysc_in[567] are subsets of keysc_in8.

This reduces kernel size by 144 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6d11be0accdaf4a42ce2a64e64201ab0670d65db.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
7a2b378232 pinctrl: renesas: r8a7791: Share HSCIF1 pin group data 
Pin group hscif1_data_e can be an alias for hscif1_data_c.

This reduces kernel size by 16 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5afdfcaa24d41ebc50af37ff5da055203744f8b5.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
292ce67a19 pinctrl: renesas: emev2: Share CF pin group data 
Pin group cf_data8 is a subset of cf_data16.

This reduces kernel size by 64 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/370d823be136cc9ead7051915a1454252a57efc4.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:57 +01:00
Geert Uytterhoeven
7c2f5298c1 pinctrl: renesas: r8a7740: Share BSC pin group data 
Pin groups bsc_data{8,16} are subsets of bsc_data32.
Pin groups bsc_rd_we{8,16} are subsets of bsc_rd_we32.

This reduces kernel size by 232 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/556873f8392b1a7d1a2cf9c10abb5e6c283f11cc.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
496da10037 pinctrl: renesas: Add generic support for resizable buses 
The VIN_DATA_PIN_GROUP() macro and vin_data{12,16,} unions are used to
define multiple VIN data groups with different numbers of lanes, while
referring to a single array of data pins, thus saving memory.

However, the same feature would be useful for other resizable buses,
like MMC, SDHI, QSPI, LCD, BSC, ...

Rework the mechanism for generic use:
  - Use the new SH_PFC_PIN_GROUP_SUBSET() helper to remove the need for
    bus-specific unions,
  - Rename VIN_DATA_PIN_GROUP() to BUS_DATA_PIN_GROUP(),
  - Rename the macro parameters to better reflect their purposes,
  - Move the macro up, where it belongs.

Update all individual pin control drivers for the above changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cccfcfd01eb8ab7a587b084c4ddbf97293bd7291.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
49a7a27425 pinctrl: renesas: Add generic support for pin group subsets 
It is fairly common for the pins in a pin group to be a subset of the
pins in another pin group.  Add a macro for defining a pin group that
refers to a subset of an array of pins.  This allows pin groups to share
pin data, and thus save memory.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b56c4257aee1eab698bae2cf7a08aa05775c0a77.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
a0894be3e0 pinctrl: renesas: Rename SH_PFC_PIN_GROUP{,_ALIAS} args 
Rename the arguments of the SH_PFC_PIN_GROUP_ALIAS() and
SH_PFC_PIN_GROUP() macros, to better reflect their purposes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/495fd5cd910d59489f4c1336e4a02da3679b5ffb.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
8d88055281 pinctrl: renesas: Reformat macros defining struct initializers 
Reformat all macros that define structure initializers, to visually
resemble structure definitions:
  - Move the opening curly brace to the previous line,
  - Move the closing curly brace to the first position,
  - Reduce indentation of the block to a single TAB, decreasing the need
    for line breaks,
  - Align backslashes for line continuation to the last TAB block where
    possible,

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/03a1eed3c4f57d7b14ef53ab49e04de10d0e383c.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
c614d12c4b pinctrl: renesas: Rename sh_pfc_soc_operations instances 
Some instances of struct sh_pfc_soc_operations are called
"<soc>_pfc_ops", others are called "<soc>_pinmux_ops" or just
"pinmux_ops".  Settle on the first variant, to avoid confusion with
"struct pinmux_ops" in the pinctrl core, and to increase consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2ab33ad1d6a20a57d16922678b78810fa55b7fc0.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
9e04a0eda8 pinctrl: renesas: r8a77470: Reduce size for narrow VIN1 channel 
The second video-in channel on RZ/G1C has only 12 data lanes, but the
pin control driver uses the vin_data union, which is meant for 24 data
lanes, thus wasting space.

Fix this by using the vin_data12 union instead.

This reduces kernel size by 96 bytes.

Fixes: 50f3f2d73e ("pinctrl: sh-pfc: Reduce kernel size for narrow VIN channels")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/52716fa89139f6f92592633edb52804d4c5e18f0.1640269757.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
efe80cdfab pinctrl: renesas: r8a7794: Add range checking to .pin_to_pocctrl() 
The .pin_to_pocctrl() implementation for R-Car E2 does not perform a
full range check, unlike on all other SoCs.  Add the range check, so the
checker can validate better the consistency of the pin control tables.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d23767ad7152327654192d7191f4b8ae19493966.1640269510.git.geert+renesas@glider.be
 2022-02-22 09:55:56 +01:00
Samuel Holland
4649b97042 pinctrl: sunxi: Use unique lockdep classes for IRQs 
This driver, like several others, uses a chained IRQ for each GPIO bank,
and forwards .irq_set_wake to the GPIO bank's upstream IRQ. As a result,
a call to irq_set_irq_wake() needs to lock both the upstream and
downstream irq_desc's. Lockdep considers this to be a possible deadlock
when the irq_desc's share lockdep classes, which they do by default:

 ============================================
 WARNING: possible recursive locking detected
 5.17.0-rc3-00394-gc849047c2473 #1 Not tainted
 --------------------------------------------
 init/307 is trying to acquire lock:
 c2dfe27c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0

 but task is already holding lock:
 c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0

 other info that might help us debug this:
  Possible unsafe locking scenario:

        CPU0
        ----
   lock(&irq_desc_lock_class);
   lock(&irq_desc_lock_class);

  *** DEADLOCK ***

  May be due to missing lock nesting notation

 4 locks held by init/307:
  #0: c1f29f18 (system_transition_mutex){+.+.}-{3:3}, at: __do_sys_reboot+0x90/0x23c
  #1: c20f7760 (&dev->mutex){....}-{3:3}, at: device_shutdown+0xf4/0x224
  #2: c2e804d8 (&dev->mutex){....}-{3:3}, at: device_shutdown+0x104/0x224
  #3: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0

 stack backtrace:
 CPU: 0 PID: 307 Comm: init Not tainted 5.17.0-rc3-00394-gc849047c2473 #1
 Hardware name: Allwinner sun8i Family
  unwind_backtrace from show_stack+0x10/0x14
  show_stack from dump_stack_lvl+0x68/0x90
  dump_stack_lvl from __lock_acquire+0x1680/0x31a0
  __lock_acquire from lock_acquire+0x148/0x3dc
  lock_acquire from _raw_spin_lock_irqsave+0x50/0x6c
  _raw_spin_lock_irqsave from __irq_get_desc_lock+0x58/0xa0
  __irq_get_desc_lock from irq_set_irq_wake+0x2c/0x19c
  irq_set_irq_wake from irq_set_irq_wake+0x13c/0x19c
    [tail call from sunxi_pinctrl_irq_set_wake]
  irq_set_irq_wake from gpio_keys_suspend+0x80/0x1a4
  gpio_keys_suspend from gpio_keys_shutdown+0x10/0x2c
  gpio_keys_shutdown from device_shutdown+0x180/0x224
  device_shutdown from __do_sys_reboot+0x134/0x23c
  __do_sys_reboot from ret_fast_syscall+0x0/0x1c

However, this can never deadlock because the upstream and downstream
IRQs are never the same (nor do they even involve the same irqchip).

Silence this erroneous lockdep splat by applying what appears to be the
usual fix of moving the GPIO IRQs to separate lockdep classes.

Fixes: a59c99d9ea ("pinctrl: sunxi: Forward calls to irq_set_irq_wake")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220216040037.22730-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-19 02:12:37 +01:00
Mans Rullgard
f3d6c538c3 pinctrl: sunxi: do not print error message for EPROBE_DEFER 
Avoid printing an error message if getting a regulator fails with
EPROBE_DEFER.  This can happen if, for example, a regulator supplying
one of the main banks is controlled by a PL pin.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20220217131737.10931-1-mans@mansr.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-19 02:09:07 +01:00
Linus Walleij
fbfc5fc351 Merge tag 'samsung-pinctrl-5.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel 
Samsung pinctrl drivers changes for v5.18

1. Fix OF reference leak in pinctrl driver probe error path.
2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks.
3. Accept devicetrees with GPIO pin bank definitions named with a
   "-gpio-bank" suffix.  This is necessary for later Samsung pinctrl
   bindings dtschema.
4. Convert Samsung pinctrl bindings to dtschema.
5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts.
6. Add support for Tesla FSD SoC.
 2022-02-19 02:05:02 +01:00
Linus Walleij
486c2d15aa Merge tag 'intel-pinctrl-v5.17-5' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes 
intel-pinctrl for v5.17-5

* Revert misplaced ID

The following is an automated git shortlog grouped by driver:

tigerlake:
 -  Revert "Add Alder Lake-M ACPI ID"
 2022-02-19 02:03:58 +01:00
Shawn Guo
c981a78944 pinctrl: qcom: qcm2290: Add GPIO wakeirq map 
It adds the map of wakeup capable GPIOs and the pins at MPM wake
controller on QCM2290, so that these GPIOs can wake up the SoC from
vlow/vmin low power mode.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20211122080938.20623-1-shawn.guo@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-19 01:59:19 +01:00
Jonathan Marek
06e12b7928 pinctrl: qcom: print egpio mode in debugfs 
When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and
the APSS TLMM settings are ignored. Reflect that in the debugfs dump.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220210131210.24605-2-jonathan@marek.ca
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-19 01:53:55 +01:00
Jonathan Marek
c74803ee45 pinctrl: qcom: sm8450: Add egpio support 
This mirrors egpio support added for sc7280. This change is necessary for
gpios 165 to 209 to be driven by APSS.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220210131210.24605-1-jonathan@marek.ca
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-19 01:53:55 +01:00
Marc Zyngier
64fd52a4d3 pinctrl: starfive: Use a static name for the GPIO irq_chip 
Drop the device name used for the GPIO irq_chip and replace it
with something static. The information is still available from
debugfs and carried as part of the irqdomain.

Suggested-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Link: https://lore.kernel.org/r/20220211092345.1093332-1-maz@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-19 01:50:23 +01:00
Linus Walleij
8d4c0d185a Merge tag 'renesas-pinctrl-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 
pinctrl: renesas: Updates for v5.18

  - Add MOST (MediaLB I/F) pins on R-Car E3 and D3,
  - Add support for the new RZ/V2L SoC,
  - Miscellaneous fixes and improvements.
 2022-02-19 01:49:03 +01:00
Andy Shevchenko
6f66db29e2 pinctrl: tigerlake: Revert "Add Alder Lake-M ACPI ID" 
It appears that last minute change moved ACPI ID of Alder Lake-M
to the INTC1055, which is already in the driver.

This ID on the other hand will be used elsewhere.

This reverts commit 258435a1c8.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 2022-02-15 19:02:46 +02:00
Sean Anderson
e9f7b9228a pinctrl: k210: Fix bias-pull-up 
Using bias-pull-up would actually cause the pin to have its pull-down
enabled. Fix this.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Fixes: d4c34d09ab ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver")
Link: https://lore.kernel.org/r/20220209182822.640905-1-seanga2@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 02:19:47 +01:00
Dan Carpenter
ba2ab85951 pinctrl: fix loop in k210_pinconf_get_drive() 
The loop exited too early so the k210_pinconf_drive_strength[0] array
element was never used.

Fixes: d4c34d09ab ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220209180804.GA18385@kili
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 02:18:35 +01:00
Jonathan Neuschäfer
603501c164 pinctrl: nuvoton: npcm7xx: Rename DS() macro to DSTR() 
The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h,
which results in a compiler warning when build-testing on ARCH=um.
Rename this driver's "DS" macro to DSTR so avoid this collision.

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b588e43ee ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220205155332.1308899-3-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 02:03:53 +01:00
Jonathan Neuschäfer
9d0f18bca3 pinctrl: nuvoton: npcm7xx: Use %zu printk format for ARRAY_SIZE() 
When compile-testing on 64-bit architectures, GCC complains about the
mismatch of types between the %d format specifier and value returned by
ARRAY_LENGTH(). Use %zu, which is correct everywhere.

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b588e43ee ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220205155332.1308899-2-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 02:03:53 +01:00
kernel test robot
9c03e49e0c pinctrl: starfive: fix semicolon.cocci warnings 
drivers/pinctrl/pinctrl-starfive.c:1029:2-3: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Reported-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20220206003735.GA94316@d6598ff186c2
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 01:47:54 +01:00
Kunihiko Hayashi
923fe8abb0 pinctrl: uniphier: Add USB device pinmux settings 
Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for
ports 0 and 1 support USB device mode.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 01:37:21 +01:00
Kunihiko Hayashi
dfc04955c8 pinctrl: uniphier: Divide pinmux group to support 1ch and 2ch I2S 
Current pinmux group for audio in/out assumes 4ch I2S case but the
UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current
ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other
ain and aout in the same way.

Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-3-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 01:37:21 +01:00
Kunihiko Hayashi
8e703784ed pinctrl: uniphier: Add missing audio pinmux settings for PXs2 SoC 
Add missing audio I/O pinmux settings for PXs2 SoC.
This adds ain1 4ch pins, ain3 and aout1.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 01:37:21 +01:00
Rayyan Ansari
d8420f5a25 pinctrl: qcom: spmi-mpp: Add PM8226 compatible 
The PM8226 provides 8 MPPs.
Add a compatible to support them.

Signed-off-by: Rayyan Ansari <rayyan@ansari.sh>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220124171538.18088-2-rayyan@ansari.sh
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-11 01:08:06 +01:00
Marc Zyngier
0d872ed9e2 pinctrl: starfive: Move PM device over to irq domain 
Move the reference to the device over to the irq domain.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Emil Renner Berthing <kernel@esmil.dk>
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
Link: https://lore.kernel.org/r/20220201120310.878267-12-maz@kernel.org
 2022-02-10 11:07:04 +00:00
Marc Zyngier
f7e53e2255 pinctrl: npcm: Fix broken references to chip->parent_device 
The npcm driver has a bunch of references to the irq_chip parent_device
field, but never sets it.

Fix it by fishing that reference from somewhere else, but it is
obvious that these debug statements were never used. Also remove
an unused field in a local data structure.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
Link: https://lore.kernel.org/r/20220201120310.878267-11-maz@kernel.org
 2022-02-10 11:07:04 +00:00
Biju Das
2e08ab0427 pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register() 
Update rzg2l_gpio_register() to use driver data for chip->names
and check for gpio-range. This allows reusing the driver for
SoC's with different port pin definitions(eg:- RZ/G2UL SoC has
fewer ports compared to RZ/G2L and port pin definitions are
different).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
5a2a1c7139 pinctrl: renesas: r8a77995: Restore pin group sort order 
Move the msiof* pin groups where they belong.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/da1018c56134b910121b085b736fe7f664b96df1.1643199959.git.geert+renesas@glider.be
 2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
8313b5e71e pinctrl: renesas: r8a7790: Restore pin function sort order 
Move the du* pin function where it belongs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f4eb545cedcd1a72f0f80ef85daf03e2e423e90f.1643199959.git.geert+renesas@glider.be
 2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
4af28d905f pinctrl: renesas: r8a7779: Restore pin function sort order 
Move the sdhi* pin functions where they belong.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f69d05a760445c8d67bedcb39cf5959333c71a1f.1643199959.git.geert+renesas@glider.be
 2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
652ef476d1 pinctrl: renesas: r8a779a0: Rename MOD_SEL2_* definitions 
Rename the MOD_SEL2_* definitions, to match the bitfield order in
IPxSRy_* definitions and in MOD_SEL* definitions in other drivers.

No changes in generated code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/4880e4cbc112ee26569bf29a21c070125461e58d.1642524603.git.geert+renesas@glider.be
 2022-02-08 09:54:44 +01:00
Biju Das
0c8fce49f2 pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled 
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin control support.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-02-08 09:54:04 +01:00
Horatiu Vultur
8fc0bfcd57 pinctrl: ocelot: Add support for ServalT SoC 
This patch adds support for ServalT pinctrl, using the ocelot driver as
basis.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220125131858.309237-3-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-02-03 00:38:28 +01:00
Martin Jücker
3652dc070b pinctrl: samsung: improve wake irq info on console 
Improve the wake irq message by also printing the bank name and hwirq
number that matches this irq number.

Signed-off-by: Martin Jücker <martin.juecker@gmail.com>
Link: https://lore.kernel.org/r/20220130232122.GA119248@adroid
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
 2022-02-01 09:13:30 +01:00
Horatiu Vultur
baf927a833 pinctrl: microchip-sgpio: Fix support for regmap 
Initially the driver accessed the registers using u32 __iomem but then
in the blamed commit it changed it to use regmap. The problem is that now
the offset of the registers is not calculated anymore at word offset but
at byte offset. Therefore make sure to multiply the offset with word size.

Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Colin Foster <colin.foster@in-advantage.com>
Fixes: 2afbbab45c ("pinctrl: microchip-sgpio: update to support regmap")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220131085201.307031-1-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-01-31 12:07:31 +01:00
Wells Lu
aa74c44be1 pinctrl: Add driver for Sunplus SP7021 
Add driver for Sunplus SP7021 SoC.

Signed-off-by: Wells Lu <wellslutw@gmail.com>
Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-01-30 02:55:41 +01:00
Qianggui Song
775214d389 pinctrl: meson: add pinctrl driver support for Meson-S4 Soc 
Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the
same register layout as the previous Meson-A1.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-01-30 02:52:45 +01:00