Since we have generic function to count GPIO controller nodes
under a given device, there is no need to open code it. Replace
custom code by gpiochip_node_count() call.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Currently compilation test fails on x86 due to name collision. The usual
way to fix that is to move both conflicting parts to their own namespaces.
Rename REG_* to MESON_REG_* as a prerequisite for enabling COMPILE_TEST.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Since we have fwnode of the first found GPIO controller assigned to the
struct gpio_chip, we may reuse it in the armada_37xx_irqchip_register().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Switch the code to use for_each_gpiochip_node() helper.
While at it, in order to avoid additional churn in the future,
switch to fwnode APIs where it makes sense.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The node is taken from the device pointer, which is supplied as a parameter,
hence no need to have a separate parameter for node. Drop redundant node
parameter in samsung_banks_of_node_get().
While at it, drop "of_" part in the samsung_banks_of_node_get() and
samsung_banks_of_node_put() function names to avoid additional churn
in the next changes.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Switch the code to use for_each_gpiochip_node() helper.
While at it, in order to avoid additional churn in the future,
do the following:
- use a temporary variable for struct device pointer to shorten a few lines
- get rid of a temporary variable for vIRQ number, assign it directly
- switch to fwnode APIs where it makes sense
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Switch the code to use for_each_gpiochip_node() helper.
While at it, in order to avoid additional churn in the future,
switch to fwnode APIs where it makes sense.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Since we have generic function to count GPIO controller nodes
under a given device, there is no need to open code it. Replace
custom code by gpiochip_node_count() call.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
It appears that almost traditionally the N variants have deviations
in the register offsets in comparison to S one. This is the case
for Intel Alder Lake as well. Fix register offsets for ADL-N variant.
Fixes: 114b610b90 ("pinctrl: alderlake: Add Intel Alder Lake-N pin controller support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Pull pin control updates from Linus Walleij:
"No core changes this time. Just new driver code and improvements!
New drivers:
- New driver for the Broadcom BCM4908 SoC.
- New subdriver for Tesla FSD (Full Self Driving) SoC, a derivative
of the Samsung Exynos pin control driver.
- New driver for the Amlogic Meson S4 SoC.
- New driver for the Sunplus SP7021 SoC.
- New driver for the Microsemi Ocelot family ServalT SoC.
- New subdriver for Intel Alder Lake-M SoC.
- New subdriver for Intel Ice Lake-N SoC, including PCH support.
- New subdriver for Renesas R8A779F0 SoC.
- New subdriver for Mediatek MT8186 SoC.
- New subdriver for NXP Freescale i.MX93 SoC.
- New driver for Nuvoton WPCM450 SoC.
- New driver for Qualcomm SC8280XP SoC.
Improvements:
- Wakeup support on Samsung Exynos850 and ExynosAutov9.
- Serious and voluminous maintenance cleanup and refactoring in the
Renesas drivers. Mainly sharing similar data between the different
SoC subdrivers.
- Qualcomm SM8450 EGPIO support.
- Drive strength support on the Mediatek MT8195.
- Add some missing groups and functions to the Ralink RT2880"
* tag 'pinctrl-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (188 commits)
pinctrl: mediatek: common-v1: fix semicolon.cocci warnings
pinctrl: nuvoton: wpcm450: Fix build error without OF
pinctrl: qcom-pmic-gpio: Add support for pm8450
dt-bindings: pinctrl: aspeed: Update gfx node in example
dt-bindings: pinctrl: rt2880: add missing pin groups and functions
pinctrl: ingenic: Fix regmap on X series SoCs
pinctrl: nuvoton: Fix return value check in wpcm450_gpio_register()
pinctrl: nuvoton: wpcm450: off by one in wpcm450_gpio_register()
pinctrl: nuvoton: wpcm450: select GENERIC_PINCTRL_GROUPS
pinctrl: nuvoton: Fix sparse warning
pinctrl: mediatek: mt8186: Account for probe refactoring
pinctrl: mediatek: common-v1: Commonize spec_ies_smt_set callback
pinctrl: mediatek: common-v1: Commonize spec_pupd callback
pinctrl: mediatek: common-v1: Use common probe function
pinctrl: mediatek: common-v1: Add common probe function
pinctrl: mediatek: paris: Unify probe function by using OF match data
pinctrl/rockchip: Add missing of_node_put() in rockchip_pinctrl_probe
pinctrl: nomadik: Add missing of_node_put() in nmk_pinctrl_probe
pinctrl: berlin: fix error return code of berlin_pinctrl_build_state()
pinctrl: qcom: Introduce sc8280xp TLMM driver
...
Pull x86 platform driver updates from Hans de Goede:
"New drivers:
- AMD Host System Management Port (HSMP)
- Intel Software Defined Silicon
Removed drivers (functionality folded into other drivers):
- intel_cht_int33fe_microb
- surface3_button
amd-pmc:
- s2idle bug-fixes
- Support for AMD Spill to DRAM STB feature
hp-wmi:
- Fix SW_TABLET_MODE detection method (and other fixes)
- Support omen thermal profile policy v1
serial-multi-instantiate:
- Add SPI device support
- Add support for CS35L41 amplifiers used in new laptops
think-lmi:
- syfs-class-firmware-attributes Certificate authentication support
thinkpad_acpi:
- Fixes + quirks
- Add platform_profile support on AMD based ThinkPads
x86-android-tablets:
- Improve Asus ME176C / TF103C support
- Support Nextbook Ares 8, Lenovo Tab 2 830 and 1050 tablets
Lots of various other small fixes and hardware-id additions"
* tag 'platform-drivers-x86-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (60 commits)
platform/x86: think-lmi: Certificate authentication support
Documentation: syfs-class-firmware-attributes: Lenovo Certificate support
platform/x86: amd-pmc: Only report STB errors when STB enabled
platform/x86: amd-pmc: Drop CPU QoS workaround
platform/x86: amd-pmc: Output error codes in messages
platform/x86: amd-pmc: Move to later in the suspend process
ACPI / x86: Add support for LPS0 callback handler
platform/x86: thinkpad_acpi: consistently check fan_get_status return.
platform/x86: hp-wmi: support omen thermal profile policy v1
platform/x86: hp-wmi: Changing bios_args.data to be dynamically allocated
platform/x86: hp-wmi: Fix 0x05 error code reported by several WMI calls
platform/x86: hp-wmi: Fix SW_TABLET_MODE detection method
platform/x86: hp-wmi: Fix hp_wmi_read_int() reporting error (0x05)
platform/x86: amd-pmc: Validate entry into the deepest state on resume
platform/x86: thinkpad_acpi: Don't use test_bit on an integer
platform/x86: thinkpad_acpi: Fix compiler warning about uninitialized err variable
platform/x86: thinkpad_acpi: clean up dytc profile convert
platform/x86: x86-android-tablets: Depend on EFI and SPI
platform/x86: amd-pmc: uninitialized variable in amd_pmc_s2d_init()
platform/x86: intel-uncore-freq: fix uncore_freq_common_init() error codes
...
The X series Ingenic SoCs have a shadow GPIO group which is at a higher
offset than the other groups, and is used for all GPIO configuration.
The regmap did not take this offset into account and set max_register
too low, so the regmap API blocked writes to the shadow group, which
made the pinctrl driver unable to configure any pins.
Fix this by adding regmap access tables to the chip info. The way that
max_register was computed was also off by one, since max_register is an
inclusive bound, not an exclusive bound; this has been fixed.
Cc: stable@vger.kernel.org
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Fixes: 6626a76ef8 ("pinctrl: ingenic: Add .max_register in regmap_config")
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20220317000740.1045204-1-aidanmacdonald.0x0@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sparse complains:
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c:626:9:
sparse: sparse: obsolete array initializer, use C99 syntax
This is because no equal sign is between the array index
and the assignments, in the macro.
Fix it up.
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pull ARM devicetree updates from Arnd Bergmann:
"After a somewhat quiet 5.17 release, the size of the DT changes is a
bit larger again. There are nine new SoC that get added, all of them
related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added
all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic:
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno:
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar:
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)"
* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
arm64: dts: n5x: drop invalid property and fix edac node name
arm64: dts: fsd: Add the MCT support
arm64: dts: stingray: Fix spi clock name
arm64: dts: ns2: Fix spi clock name
ARM: dts: rockchip: Update regulator name for PX3
ARM: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
ARM: dts: at91: sama7g5: Add NAND support
ARM: dts: at91: sama7g5: add eic node
ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
arm64: dts: lg: align pl330 node name with dtschema
arm64: dts: lg: add dma-cells to pl330 node
arm64: dts: juno: align pl330 node name with dtschema
arm64: dts: broadcom: Fix sata nodename
arm64: dts: n5x: add sdr edac support
arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
dt-bindings: usb: dwc2: add disable-over-current
...
All of the MediaTek pinctrl drivers registering with pinctrl-mtk-common
that are offering a .spec_ies_smt_set() callback are declaring their
own function which is doing exactly the same on all drivers: calling
mtk_pconf_spec_set_ies_smt_range() with their struct and a simple check.
Commonize this callback by adding the ies and smt structure pointers
to struct mtk_pinctrl_devdata and changing the callback signature to
take it.
Removing the callback and checking for the existance of the spec_smt
and/or spec_ies data would allow us to staticize the function
mtk_pconf_spec_set_ies_smt_range(), but this solution was avoided as
to keep flexibility, as some SoCs may need to perform a very different
operation compared to what this commonized function is doing.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220222111144.20796-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most of the mediatek pinctrl drivers are calling mtk_pctrl_init() and
passing only a pointer to struct mtk_pinctrl_devdata, as the regmap
handle it passed from device-tree, with the exception of mt6397.
For all of the drivers that don't require passing a struct regmap
pointer from a parent device, simplify the probe mechanism by assigning
the required structure as match data and use mtk_pctrl_common_probe()
as their probe function.
While at it, also collapse the of_device_id entries to a single line,
as they all fit in max 83 columns, which is acceptable.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220222111144.20796-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All of the SoCs using Paris pinctrl are defining a custom probe
function that is simply calling mtk_paris_pinctrl_probe() passing
a pointer to the SoC specific mtk_pin_soc structure and nothing else.
Simplify the probe mechanism across all pinctrl drivers that are
using pinctrl-paris by passing the specific mtk_pin_soc as match
data and using function mtk_paris_pinctrl_probe as a common probe
function for all of them.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220222111144.20796-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Right now, when a gpio value is set, the actual hardware pin gets set
asynchronously. When linux write the output register, it takes some time
until it is actually propagated to the output shift registers. If that
output port is connected to an I2C mux for example, the linux driver
assumes the I2C bus is already switched although it is not.
Fortunately, there is a single shot mode with a feedback: you can
trigger the single shot and the hardware will clear that bit once it has
finished the clocking and strobed the load signal of the shift
registers. This can take a considerable amount of time though.
Measuremens have shown that it takes up to a whole burst cycle gap which
is about 50ms on the largest setting. Therefore, we have to mark the
output bank as sleepable. To avoid unnecessary waiting, just trigger the
single shot if the value was actually changed.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-6-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make sgpio_output_set() return an error value. Don't just ignore the
return value of any regmap access but propagate it to our callers. Even
if the accesses never fail, this is a preparation patch to add single
shot mode where we need to poll a bit and thus we might get -ETIMEDOUT.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-5-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The interrupt ack register has the usual "write one to clear" semantics.
No read-modify-write is required here.
This is also a preparation patch to change the sgpio_clrsetbits() to use
regmap_update_bits() which don't write the value if it is not changed.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-3-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
