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28631 Commits

Author SHA1 Message Date
Matthew Auld
97c8ef443a drm/i915/selftests: handle object rounding 
Ensure we account for any object rounding due to min_page_size
restrictions.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206112539.3149779-4-matthew.auld@intel.com
 2021-12-08 10:25:27 +00:00
Matthew Auld
31d70749bf drm/i915/migrate: fix length calculation 
No need to insert PTEs for the PTE window itself, also foreach expects a
length not an end offset, which could be gigantic here with a second
engine.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206112539.3149779-3-matthew.auld@intel.com
 2021-12-08 10:25:26 +00:00
Matthew Auld
08c7c122ad drm/i915/migrate: fix offset calculation 
Ensure we add the engine base only after we calculate the qword offset
into the PTE window.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206112539.3149779-2-matthew.auld@intel.com
 2021-12-08 10:25:25 +00:00
Matthew Auld
8eb7fcce34 drm/i915/migrate: don't check the scratch page 
The scratch page might not be allocated in LMEM(like on DG2), so instead
of using that as the deciding factor for where the paging structures
live, let's just query the pt before mapping it.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206112539.3149779-1-matthew.auld@intel.com
 2021-12-08 10:25:24 +00:00
Ville Syrjälä
d4a2393049 drm/i915: Allow cdclk squasher to be reconfigured live 
Supposedly we should be able to change the cdclk squasher waveform
even when many pipes are active. Make it so.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-6-mika.kahola@intel.com
 2021-12-07 16:54:07 +02:00
Mika Kahola
77ab3a1ecb drm/i915/display/dg2: Read CD clock from squasher table 
To calculate CD clock with squasher unit, we set CD clock ratio to fixed value of 34.
The CD clock value is read from CD clock squasher table.

BSpec: 54034

v2: Read ratio from register (Ville)
    Drop unnecessary local variable (Ville)
    Get CD clock from the given table
v3: Calculate CD clock frequency based on waveform bit pattern (Ville)
[v4: vsyrjala: Actually do a proper blind readout from the hardware]
[v5: vsyrjala: Use has_cdclk_squasher()]

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-5-mika.kahola@intel.com
 2021-12-07 16:54:06 +02:00
Mika Kahola
2060a6895b drm/i915/display/dg2: Set CD clock squashing registers 
Set CD clock squashing registers based on selected CD clock.

v2: use slk_cdclk_decimal() to compute decimal values instead of a
    specific table (Ville)
    Set waveform based on CD clock table (Ville)
    Drop unnecessary local variable (Ville)
v3: Correct function naming (Ville)
    Correct if-else structure (Ville)
[v4: vsyrjala: Fix spaces vs. tabs]
[v5: vsyrjala: Fix cd2x divider calculation (Uma),
               Add warn to waveform lookup (Uma),
               Handle bypass freq in waveform lookup,
               Generalize waveform handling in bxt_set_cdclk()]

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-4-mika.kahola@intel.com
 2021-12-07 16:54:05 +02:00
Mika Kahola
ba884a4117 drm/i915/display/dg2: Sanitize CD clock 
In case of CD clock squashing the divider is always 1. We don't
need to calculate the divider in use so let's skip that for DG2.

v2: Drop unnecessary local variable (Ville)
v3: Avoid if-else structure (Ville)
[v4: vsyrjala: Fix cd2x divider calculation (Uma),
               Introduce has_cdclk_squasher()]

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-3-mika.kahola@intel.com
 2021-12-07 16:54:05 +02:00
Mika Kahola
2fb352fa62 drm/i915/display/dg2: Introduce CD clock squashing table 
For CD clock squashing method, we need to define corresponding CD clock table for
reference clocks, dividers and ratios for all CD clock options.

BSpec: 54034

v2: Add CD squashing waveforms as part of CD clock table (Ville)
v3: Waveform is 16 bits wide (Ville)
[v4: vsyrjala: Nuke the non-squasher based table,
               Set .divider=2 for consistency,
	       Pack intel_cdclk_vals a bit nicer]
v5: Fix error in waveform value (Swati)
v6 (Lucas): Rebase on upstream
v7 (MattR): Drop 40.8, 81.6, and 122.4 MHz frequencies to reflect new
    bspec update.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-2-mika.kahola@intel.com
 2021-12-07 16:54:03 +02:00
Bruce Chang
491fe469ad drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftests 
Follow up on below commit, to increase the timeout further on new
platforms, to accomodate the additional time required for the completion
of guc submissions for numerous requests created in loop.

commit 5e076529e2
Author: Matthew Brost <matthew.brost@intel.com>
Date:   Mon Jul 26 20:17:03 2021 -0700

    drm/i915/selftests: Increase timeout in i915_gem_contexts selftests

Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211207003845.12419-1-yu.bruce.chang@intel.com
 2021-12-07 20:19:49 +05:30
Jani Nikula
fbf8b5dc6d drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpers 
Localize HOBL and low vswing VBT lookups to a couple of small helpers,
and get rid of a bunch of local variables.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211203131318.2885969-1-jani.nikula@intel.com
 2021-12-07 10:59:22 +02:00
Jani Nikula
61b98486e4 drm/i915/snps: use div32 version of MPLLB word clock for UHBR 
The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.

Bspec: 53880, 54128
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com
 2021-12-07 10:41:07 +02:00
Uma Shankar
1c7ab5affa drm/i915/xelpd: Add Pipe Color Lut caps to platform config 
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.

v2: Updated lut size for 10bit gamma, added lut_tests (Ville)

v3: Dropped the gamma lut tests fields (Ville)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-4-uma.shankar@intel.com
 2021-12-07 12:50:31 +05:30
Uma Shankar
17815f624a drm/i915/xelpd: Enable Pipe Degamma 
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.

v2: Added a helper for degamma lut size (Ville)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-3-uma.shankar@intel.com
 2021-12-07 12:50:31 +05:30
Uma Shankar
e83c18cffa drm/i915/xelpd: Enable Pipe color support for D13 platform 
Enable pipe color support for Display 13 platforms. Currently
limit to just 10bit gamma and later extend it for logarithmic
gamma, once the new UAPI is agreed by community and implemented
by a userspace consumer.

v2: Updated dev_priv to i915 (Ville)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-2-uma.shankar@intel.com
 2021-12-07 12:50:30 +05:30
Madhumitha Tolakanahalli Pradeep
5d50c8d7ed drm/i915/dmc: Change max DMC FW size on ADL-P 
Increase the max size of DMC on ADL-P to account for support of new
features in the current/upcoming DMC versions.

Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211207023718.322349-1-madhumitha.tolakanahalli.pradeep@intel.com
 2021-12-06 23:05:45 -08:00
Michael Cheng
5f97816762 drm/i915: Introduce new macros for i915 PTE 
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).

Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.

v2(Michael Cheng): Use GEN8_ instead of I915_

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
[ Move defines together with other GEN8 defines ]
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206215245.513677-2-michael.cheng@intel.com
 2021-12-06 22:21:03 -08:00
Clint Taylor
dfb924e339 drm/i915/adlp: Remove require_force_probe protection 
Remove force probe protection from ADL_P platform. Did not obsevre
warnings, errors, flickering or any visual defects while doing ordinary
tasks like browsing and editing documents in a two monitor setup.

For more info drm-tip idle run results :
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211204010140.22839-1-clinton.a.taylor@intel.com
 2021-12-03 17:26:27 -08:00
Dan Carpenter
8722ded49c drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer() 
Originally "out_fence" was set using out_fence = sync_file_create() but
which returns NULL, but now it is set with out_fence = eb_requests_create()
which returns error pointers.  The error path needs to be modified to
avoid an Oops in the "goto err_request;" path.

Fixes: 544460c338 ("drm/i915: Multi-BB execbuf")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211202044831.29583-1-matthew.brost@intel.com
 2021-12-03 11:47:29 -08:00
Jakub Kicinski
8581fd402a treewide: Add missing includes masked by cgroup -> bpf dependency 
cgroup.h (therefore swap.h, therefore half of the universe)
includes bpf.h which in turn includes module.h and slab.h.
Since we're about to get rid of that dependency we need
to clean things up.

v2: drop the cpu.h include from cacheinfo.h, it's not necessary
and it makes riscv sensitive to ordering of include files.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Acked-by: Krzysztof Wilczyński <kw@linux.com>
Acked-by: Peter Chen <peter.chen@kernel.org>
Acked-by: SeongJae Park <sj@kernel.org>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/all/20211120035253.72074-1-kuba@kernel.org/  # v1
Link: https://lore.kernel.org/all/20211120165528.197359-1-kuba@kernel.org/ # cacheinfo discussion
Link: https://lore.kernel.org/bpf/20211202203400.1208663-1-kuba@kernel.org
 2021-12-03 10:58:13 -08:00
Tejas Upadhyay
af10ec31a8 drm/i915/adl_p: Add ddc pin mapping 
From VBT, ddc pin info suggests the following mapping:
    VBT                                    DRIVER
    DDI TC1->ddc_pin=3 should translate to PORT_TC1->0x9
    DDI TC2->ddc_pin=4 should translate to PORT_TC2->0xa
    DDI TC3->ddc_pin=5 should translate to PORT_TC3->0xb
    DDI TC4->ddc_pin=6 should translate to PORT_TC4->0xc

Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI C and DDI TC1 info.

Bspec:20124

v2:
  - Changed Author to Tejas Upadhyay

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211203073720.3823371-1-ravitejax.goud.talla@intel.com
 2021-12-03 10:21:36 -08:00
Raviteja Goud Talla
67b858dd89 drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() 
Bspec page says "Reset: BUS", Accordingly moving w/a's:
Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init()
Which will resolve guc enabling error

v2:
  - Previous patch rev2 was created by email client which caused the
    Build failure, This v2 is to resolve the previous broken series

Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211203145603.4006937-1-ravitejax.goud.talla@intel.com
 2021-12-03 09:51:38 -08:00
Ville Syrjälä
b1e4747259 drm/i915: Get rid of the "sizes are 0 based" stuff 
Replace the "sizes are 0 based" stuff with just straight
up -1 where needed. Less confusing all around.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-4-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
 2021-12-03 19:18:53 +02:00
Ville Syrjälä
812e338619 drm/i915/fbc: Pimp the FBC debugfs output 
Now that each plane tracks its own no_fbc_reason we can print that
out in debugfs, and we can also show which plane is currently
selected for FBC duty.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-21-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2021-12-03 19:15:01 +02:00
Ville Syrjälä
d5ba72f3c1 drm/i915/fbc: No FBC+double wide pipe 
FBC and double wide pipe are mutually exclusive. Disable FBC when
we have to resort to double wide.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-20-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:26:36 +02:00
Ville Syrjälä
d3e27f7c51 drm/i915/fbc: s/parms/fbc_state/ 
Rename the 'params' to just fbc state.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-19-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:26:25 +02:00
Ville Syrjälä
0cb9f228bc drm/i915/fbc: Move plane pointer into intel_fbc_state 
Currently we track the FBC plane as a pointer under intel_fbc
and also as a i9xx_plane_id under intel_fbc_state. Just store
the pointer once in the fbc state.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-18-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:25:21 +02:00
Ville Syrjälä
f4cfdbb02c drm/i915/fbc: Nuke state_cache 
fbc->state_cache has now become useless. We can simply update
the reg params directly from the plane/crtc states during
__intel_fbc_enable().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-17-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:23:47 +02:00
Ville Syrjälä
b156def991 drm/i915/fbc: Disable FBC fully on FIFO underrun 
Currently a FIFO underrun just causes FBC to be deactivated,
and later checks then prevent it from being reactivated. We
can simpify our lives a bit by logically disabling FBC on
FIFO underruns. This avoids the funny intermediate state where
FBC is logically enabled but can't actually be activated.

v2: intel_wait_for_vblank() is no more

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-16-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:23:38 +02:00
Ville Syrjälä
98009fd73b drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane() 
Don't really see a good reason why we can't just do the vgpu and
modparam checks already in intel_fbc_check_plane().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-15-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:16:01 +02:00
Ville Syrjälä
606754fdcb drm/i915/fbc: Allocate intel_fbc dynamically 
In the future we may have more than one FBC instance on some
platforms. So let's just allocate it dynamically. This also
lets us fully hide the implementation from prying eyes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-14-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:13:21 +02:00
Ville Syrjälä
825bd8335e drm/i915/fbc: Introduce intel_fbc_add_plane() 
In order to better encapsulate the FBC implementation
introduce a small helper to do the plane<->FBC instance
association.

We'll also try to structure the plane init code such
that introducing multiple FBC instances will be easier
down the line.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-13-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:13:04 +02:00
Ville Syrjälä
d2de8ccfb2 drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c 
In order to encapsulate FBC harder let's just move the debugfs
stuff into intel_fbc.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-12-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
 2021-12-03 13:12:47 +02:00
Ville Syrjälä
32024bb85e drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff 
The underrun code doesn't need to know any details about FBC, so
just pass in the whole device rather than a specific FBC instance.
We could make this a bit more fine grained by also passing in the
pipe to intel_fbc_handle_fifo_underrun_irq() and letting the FBC
code figure which FBC instance (if any) is active on said pipe.
But that seems a bit overkill for this so don't bother.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-11-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:12:30 +02:00
Ville Syrjälä
62d4874bee drm/i915/fbc: Flatten __intel_fbc_pre_update() 
Use an early return to flatten most of __intel_fbc_pre_update().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-10-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:12:19 +02:00
Ville Syrjälä
004f80f91a drm/i915/fbc: Track FBC usage per-plane 
In the future we may have multiple planes on the same pipe
capable of using FBC. Prepare for that by tracking FBC usage
per-plane rather than per-crtc.

v2: s/intel_get_crtc_for_pipe/intel_crtc_for_pipe/

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-9-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 13:12:06 +02:00
Ville Syrjälä
6e4d2e45ef drm/i915/fbc: Pass around FBC instance instead of crtc 
Pass the FBC instance instead of the crtc to a bunch of places.

We also adjust intel_fbc_post_update() to do the
intel_fbc_get_reg_params() things instead of doing it from the lower
level function (which also gets called for front buffer tracking).
Nothing in there will change during front buffer updates.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-8-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:50:16 +02:00
Ville Syrjälä
e1521cbd27 drm/i915/fbc: Reuse the same struct for the cache and params 
The FBC state cache and params are now nearly identical. Just
use the same structure for both.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-7-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:50:05 +02:00
Ville Syrjälä
873c995a40 drm/i915/fbc: Nuke more FBC state 
There isn't a good reason why we'd have to cache all this
plane state stuff in the FBC state. Instead we can just
pre-calculate what FBC will really need.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-6-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:49:54 +02:00
Ville Syrjälä
266790871e drm/i915/fbc: Relocate intel_fbc_override_cfb_stride() 
Move intel_fbc_override_cfb_stride() next to its cousins.
Helps with later patches.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-5-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:49:43 +02:00
Ville Syrjälä
2e6c99f886 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache 
There's no need to store all this stuff in intel_fbc_state_cache.
Just check it all against the plane/crtc states and store only
what we need. Probably more should get nuked still, but this
is a start.

So what we'll do is:
- each plane will check its own state and update its local
  no_fbc_reason
- the per-plane no_fbc_reason (if any) then gets propagated
  to the cache->no_fbc_reason while doing the actual update
- fbc->no_fbc_reason gets updated in the end with either
  the value from the cache or directly from frontbuffer
  tracking

It's still a bit messy, but should hopefuly get cleaned up
more in the future. At least now we can observe each plane's
reasons for rejecting FBC now more consistently, and we don't
have so mcuh redundant state store all over the place.

v2: store no_fbc_reason per-plane instead of per-pipe

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-4-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:49:33 +02:00
Ville Syrjälä
b6e201f5f1 drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit() 
No reason to burden the caller with the details on how the minimum
compression limit is calculated, so just pass in the whole plane
state instead of just the cpp value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-3-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:49:23 +02:00
Ville Syrjälä
248e251567 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage 
The ilk fbc watermark computation uses intel_fbc_is_active() which
is racy since we don't know whether FBC will be enabled or not at
some point. So let's just assume it will be if both HAS_FBC()
and the modparam agree.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124113652.22090-2-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
 2021-12-03 12:49:14 +02:00
Ville Syrjälä
d96c5ed0e3 drm/i915: Rename PLANE_CUS_CTL Y plane bits 
Rename the PLANE_CUS_CTL Y plane selection bits to actually
say "Y plane".

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-6-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
 2021-12-03 12:49:02 +02:00
Ville Syrjälä
62f887ae46 drm/i915: Rename plane YUV order bits 
Rename the YUV byte order bits to be a bit more consistent.

v2: Deal with gvt

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-3-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
 2021-12-03 12:49:02 +02:00
Ville Syrjälä
f84b336a2f drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio 
Let's just stick to 32bit mmio accesses so we can get rid
of the bare "uncore" reg access in display code. The register
are defined as 32bit in the spec anyway.

We could define a 64bit "de" variant I suppose, but doesn't
really make much sense just for this one case, and when we
start to use the DSB for this stuff we'd also need another
64bit variant for that. Just easier to do 32bit always.

While at it we can reorder stuff a bit so that we write the
registers in order of increasing offset (more or less).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-2-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
 2021-12-03 12:49:02 +02:00
Jani Nikula
15162c5a36 drm/i915/display: stop including i915_drv.h from intel_display_types.h 
Break the dependency on i915_drv.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ee740f494e416d875e057c2eda585f4e66d65500.1638366969.git.jani.nikula@intel.com
 2021-12-03 11:46:33 +02:00
Jani Nikula
726a2d779f drm/i915/display: convert dp_to_i915() to a macro 
Avoid looking into the guts of struct drm_i915_private in
headers. Again, converting an inline function to a macro is less than
ideal, but avoids having to pull in i915_drv.h just for the to_i915()
part.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ed6c43455d13c90ebfed442b196625af5e6ede88.1638366969.git.jani.nikula@intel.com
 2021-12-03 11:39:14 +02:00
Jani Nikula
5734c1774d drm/i915: move enum hpd_pin to intel_display.h 
It's not the ideal location, but a better alternative than
i915_drv.h. The goal is to break the intel_display_types.h to i915_drv.h
dependency.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9f882eff78cdc6b28c18e73f5e53f57e413240dc.1638366969.git.jani.nikula@intel.com
 2021-12-03 11:33:37 +02:00
Jani Nikula
f83974a408 drm/i915: split out intel_pm_types.h 
This is far from ideal, but it reduces the i915_drv.h dependency from
intel_display_types.h. Maybe in the future we'll need a better split.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c6c60d9a8f6dcd1fa2f4b187000c5bb6843a1371.1638366969.git.jani.nikula@intel.com
 2021-12-03 11:28:12 +02:00