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11170 Commits

Author SHA1 Message Date
Jiansong Chen
4759f8871f drm/amdgpu: enable hdp CG and LS for navy_flounder 
Enable hdp CG and LS by setting the corresponding flags.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
92c737561c drm/amdgpu: enable mc CG and LS for navy_flounder 
Enable mc CG and LS by setting the corresponding flags.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
47fc894a87 drm/amdgpu: enable athub/mmhub PG for navy_flounder 
Enable athub/mmhub PG by setting the corresponding flags.
Actually the enablement is exercised by PMFW.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Bhawanpreet Lakha
a6c5308f2a drm/amd/display: add DC support for navy flounder 
Plumb DC support for navy flounder through.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:26 -04:00
Jiansong Chen
cf4554fada drm/amdgpu: support athub cg setting for navy_flounder 
navy_flounder has athub ip v2.1.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:25 -04:00
Jiansong Chen
40582e670f drm/amdgpu: enable GFX clock gating for navy_flounder 
Enable GFX MGCG, CGCG and 3DCG for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:21 -04:00
Boyuan Zhang
00740df995 drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounder 
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:17 -04:00
Boyuan Zhang
c6e9dd0ea8 drm/amdgpu: enable VCN3.0 DPG for navy_flounder 
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:14 -04:00
Boyuan Zhang
ebb06097ee drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder 
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:12 -04:00
Jiansong Chen
c5b6c914d2 drm/amdgpu: enable cp_fw_write_wait for navy_flounder 
It's the same with sienna_cichlid, cp fw for navy_flounder
can support WAIT_REG_MEM packet.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:09 -04:00
Boyuan Zhang
290b4ad592 drm/amdgpu: add vcn ip block for navy_flounder 
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:06 -04:00
Boyuan Zhang
5cc07534d8 drm/amdgpu: add navy_flounder vcn firmware support 
Add navy_flounder to vcn family

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:04 -04:00
Jiansong Chen
41e3b1c13f drm/amdgpu/gfx10: add gc golden setting for navy_flounder 
Add gc golden setting for navy_flounder

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:02 -04:00
Jiansong Chen
f081e6971b drm/amdgpu: use front door firmware loading for navy_flounder 
Same as other navi asics.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:52 -04:00
Jiansong Chen
7420eab23b drm/amdgpu: add psp block for navy_flounder 
Add psp and smu block for navy_flounder with
psp firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:50 -04:00
Jiansong Chen
c82b38ec2e drm/amdgpu: add psp support for navy_flounder 
Currently skip ASD FW loading and ih reroute per
sienna_cichlid.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:47 -04:00
Jiansong Chen
f4497d1029 drm/amdgpu: add smu block for navy_flounder 
Add SMU block for navy_flounder with direct
firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:44 -04:00
Jiansong Chen
922783755b drm/amdgpu: add gmc cg support for navy_flounder 
The athub version used for navy_flounder is v2.1.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:38 -04:00
Jiansong Chen
8f8463dddc drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder 
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP
with sienna_cichlid.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:35 -04:00
Tao Zhou
c4a8b80286 drm/amdgpu: configure navy_flounder gfx according to gfx 10.3 
The gfx version of navy_flounder is 10.3, identical to
sienna_cichlid, follow the way of sienna_cichlid.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:33 -04:00
Jiansong Chen
5404f07359 drm/amdgpu: add virtual display support for navy_flounder. 
Virtual display support for bring up and virtualization.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:29 -04:00
Jiansong Chen
df2d15df04 drm/amdgpu: add sdma ip block for navy_flounder 
Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:26 -04:00
Jiansong Chen
885eb3fad6 drm/amdgpu: add gfx ip block for navy_flounder 
since navy_flounder has similar gc IP version with
sienna_cichlid, follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:23 -04:00
Jiansong Chen
026c396b41 drm/amdgpu: add ih ip block for navy_flounder 
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:19 -04:00
Jiansong Chen
fc8f07da1f drm/amdgpu: add gmc ip block for navy_flounder 
navy_flounder has similar gc IP version with sienna_cichlid,
follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:14 -04:00
Jiansong Chen
8515e0a489 drm/amdgpu: add common ip block for navy_flounder 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:11 -04:00
Jiansong Chen
f097ff15cd drm/amdgpu: add support on mmhub for navy_flounder 
navy_flounder has the same mmhub IP version with sienna_cichlid,
follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:09 -04:00
Jiansong Chen
c8c959f601 drm/amdgpu: initialize IP offset for navy_flounder 
since navy_flounder has the same ip offset with sienna_cichlid,
follow sienna_cichlid setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:07 -04:00
Jiansong Chen
543aa2595c drm/amdgpu/soc15: add support for navy_flounder 
Add soc support.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:00 -04:00
Jiansong Chen
d463d8c964 drm/amdgpu/gfx10: add clockgating support for navy_flounder 
Same as navi10.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:58 -04:00
Jiansong Chen
0287ac57b5 drm/amdgpu/gmc10: add navy_flounder support 
Same as navi10.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:53 -04:00
Jiansong Chen
6501019304 drm/amdgpu/gfx10: add support for navy_flounder firmware 
Declare the gfx/compute firmwares.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:50 -04:00
Jiansong Chen
41f446bf52 drm/amdgpu: set asic family and ip blocks for navy_flounder 
Add the asic family and IP blocks for navy flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:48 -04:00
Jiansong Chen
47eb83d9a6 drm/amdgpu: set fw load type for navy_flounder 
Currently navy_flounder only supports backdoor loading type.
Will switch to psp load type when psp is ready.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:45 -04:00
Jiansong Chen
120eb83336 drm/amdgpu: add navy_flounder gpu info firmware 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:43 -04:00
Jiansong Chen
ddd8fbe77d drm/amdgpu: add navy_flounder asic type 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:39 -04:00
Huang Rui
6565547113 drm/amdgpu: expand to add multiple trap event irq id 
Sienna_cichlid has four sdma instances, but other chips don't.
So we need expand to add multiple trap event irq id in sdma
v5.2.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:35 -04:00
Jack Zhang
c8466cc0d2 drm/amd/sriov skip vcn powergating and dec_ring_test 
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.

2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.

V2: delete unneccessary white lines and refine implementation.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:28 -04:00
John Clements
a330272936 drm/amdgpu: correct ta header v2 ucode init start address 
resolve bug calculating fw start address within binary

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:18 -04:00
Jack Zhang
1f61a43fce drm/amd/sriov porting sriov cap to vcn3.0 
1.In early_init and for sriov, hardcode
  harvest_config=0, enc_num=1

2.sw_init/fini
  alloc & free mm_table for sriov
  doorbell setting for sriov

3.hw_init/fini
  Under sriov, add start_sriov to config mmsch
  Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings.

4.Implementation for vcn_v3_0_start_sriov

V2:Clean-up some uneccessary funciton declaration.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:11 -04:00
Jack Zhang
7ddb4d6c43 drm/amd/sriov add mmsch_v3 interface 
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch
to set the World Switch for MM appropriately. This patch add
the interface for mmsch_v3.0.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:45:05 -04:00
Jack Zhang
fc30e840dc drm/amdgpu: optimize rlcg write for gfx_v10 
For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:59 -04:00
Jack Zhang
c45fbe1bd5 drm/amd/sriov skip jped ip block and close pgcg flags 
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:53 -04:00
Evan Quan
42f75c849f drm/amd/powerplay: drop unused APIs and parameters 
Leftover of previous performance level setting cleanups.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:43:48 -04:00
Wenhui Sheng
273da6ff7c drm/amdgpu: add module parameter choose reset mode 
Default value is auto, doesn't change
original reset method logic.

v2: change to use parameter reset_method
v3: add warn msg if specified mode isn't supported

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:42:01 -04:00
Wenhui Sheng
311531f087 drm/amdgpu: enable mode1 reset 
For sienna cichlid, add mode1 reset path for sGPU.

v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
v3: split emergency restart logic to a new patch

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:41:54 -04:00
Wenhui Sheng
bb5c7235ea drm/amdgpu: RAS emergency restart logic refine 
If we are in RAS triggered situation and
BACO isn't support, emergency restart is needed,
and this code is only needed for some specific
cases(vega20 with given smu fw version).

After we add smu mode1 reset for sienna cichlid, we
need to share AMD_RESET_METHOD_MODE1 with psp mode1 reset,
so in amdgpu_device_gpu_recover, we need differentiate
which mode1 reset we are using, then decide if it's
a full reset and then decide if emergency restart is needed,
the logic will become much more complex.

After discussion with Hawking, move emergency restart logic
to an independent function.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:41:47 -04:00
Wenhui Sheng
ea8139d8d5 drm/amd/powerplay: add SMU mode1 reset 
From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.

v2: add mode1 reset dpm interface
v3: change maro name

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:41:32 -04:00
Xiaojie Yuan
05051496b2 drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr() 
"u64 *wptr" points to the the wptr value in write back buffer and
"*wptr = (*wptr) >> 2;" results in the value being overwritten each time
when ->get_wptr() is called.

umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and
decode ring content and it is affected by this issue.

fix and simplify the logic similar as sdma_v4_0_ring_get_wptr().

v2: fix for sdma5.2 as well
v3: drop sdma 5.2 changes for 5.8 and stable

Suggested-by: Le Ma <le.ma@amd.com>
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2020-07-14 15:42:17 -04:00
Jack Xiao
d845a2051b drm/amdgpu: fix preemption unit test 
Remove signaled jobs from job list and ensure the
job was indeed preempted.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-14 15:09:07 -04:00