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531 Commits

Author SHA1 Message Date
Biju Das
03fa6e4b26 clk: renesas: r9a07g044: Add USB clocks/resets 
Add clock/reset entries for USB PHY control, USB2.0 host and device.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210630073013.22415-5-biju.das.jz@bp.renesas.com
[geert: s/usb0_device/usb0_func]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:53 +02:00
Biju Das
eb829e549b clk: renesas: r9a07g044: Add DMAC clocks/resets 
Add DMAC clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:53 +02:00
Biju Das
1962dd36db clk: renesas: r9a07g044: Add I2C clocks/resets 
Add I2C{0,1,2,3} clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-9-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:53 +02:00
Kieran Bingham
c346ff5ccc clk: renesas: r8a779a0: Add the DSI clocks 
The DSI clock is incorrectly defined as a fixed clock. This
demonstrates itself as the dsi-encoders failing to correctly enable and
start their PPI and HS clocks internally, and causes failures.

Move the DSI parent clock to match the updates in the BSP, which
resolves the initialisation procedures.

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Fixes: 17bcc8035d ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Link: https://lore.kernel.org/r/20210622232711.3219697-3-kieran.bingham@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Kieran Bingham
417ed58dfc clk: renesas: r8a779a0: Add the DU clock 
The DU clock is added to the S3D1 clock parent. The Renesas BSP lists
S2D1 as the clock parent, however there is no S2 clock on this platform.

S3D1 is chosen as a best effort guess and demonstrates functionality but
is not guaranteed to be correct.

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Link: https://lore.kernel.org/r/20210622232711.3219697-2-kieran.bingham@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Geert Uytterhoeven
d23fcff145 clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic 
As RZ/G2 SoCs do not support DVFS, the "iic-dvfs" module was renamed to
"iic-pmic" in the RZ/G Series, 2nd Generation User’s Manual: Hardware
Rev. 1.00.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/3e549b41989ff2797b998a1c749c9f607845f44a.1624016693.git.geert+renesas@glider.be
 2021-07-19 10:53:52 +02:00
Lad Prabhakar
1606e81543 clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() 
Fix clock index out of range check for module clocks in
rzg2l_cpg_clk_src_twocell_get().

Fixes: ef3c613ccd ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210617155432.18827-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Dan Carpenter
e37868f144 clk: renesas: rzg2l: Avoid mixing error pointers and NULL 
These functions accidentally return both error pointers and NULL when
there is an error.  It doesn't cause a problem but it is confusing and
seems unintentional.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/YMtY7nOtqEvTokh7@mwanda
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Dan Carpenter
36aaa3a0d9 clk: renesas: rzg2l: Fix a double free on error 
The "pll_clk" and "clock" pointers are allocated with devm_kzalloc() so
freeing them with kfree() will lead to a double free.  This would only
happen if probe failed, and the system is not bootable.

Fixes: ef3c613ccd ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/YMtYs7LVveYH4eRe@mwanda
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Yang Li
97c2975559 clk: renesas: rzg2l: Fix return value and unused assignment 
Currently the function returns NULL on error, so exact error code is
lost.  This patch changes return convention of the function to use
ERR_PTR() on error instead.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1623896524-102058-1-git-send-email-yang.lee@linux.alibaba.com
[geert: Drop curly braces]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Yang Li
d42d57fe86 clk: renesas: rzg2l: Remove unneeded semicolon 
Eliminate the following coccicheck warning:
./drivers/clk/renesas/renesas-rzg2l-cpg.c:299:2-3: Unneeded semicolon

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1623749970-38020-1-git-send-email-yang.lee@linux.alibaba.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-19 10:53:52 +02:00
Biju Das
c3e67ad6f5 dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions 
Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx
and RZ/G2L HW(Rev.0.50) manual.

Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and
separate reset from module clocks in order to handle them efficiently.

Update the SCIF0 clock and reset index in the SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com
[geert: Squashed 3 commits]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-12 10:52:03 +02:00
Biju Das
668756f729 clk: renesas: r9a07g044: Add P2 Clock support 
Add support for P2 clock which is sourced from pll3_div2_4_2.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-12 10:52:03 +02:00
Biju Das
fd8c3f6c36 clk: renesas: r9a07g044: Fix P1 Clock 
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions for P1.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-12 10:52:03 +02:00
Biju Das
e93c137361 clk: renesas: r9a07g044: Rename divider table 
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
can be reused.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-12 10:52:03 +02:00
Biju Das
2fa9fd69b3 clk: renesas: rzg2l: Add multi clock PM support 
Add multi clock PM support for cpg driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-07-12 10:52:03 +02:00
Lad Prabhakar
17f0ff3d49 clk: renesas: Add support for R9A07G044 SoC 
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.

Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@renesas.com>.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-06-10 15:46:46 +02:00
Lad Prabhakar
ef3c613ccd clk: renesas: Add CPG core wrapper for RZ/G2L SoC 
Add CPG core wrapper for RZ/G2L family.

Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@renesas.com>.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-06-10 15:46:17 +02:00
Kuninori Morimoto
790c06cc5d clk: renesas: r8a77995: Add ZA2 clock 
R-Car D3 ZA2 clock is from PLL0D3 or S0,
and it can be controlled by ZA2CKCR.
It is needed for R-Car Sound, but is not used so far.
Using default settings is very enough at this point.
This patch adds it by DEF_FIXED().

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pmxclrmy.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-05-27 15:27:28 +02:00
Geert Uytterhoeven
3f6ecaf1ca clk: renesas: cpg-mssr: Make srstclr[] comment block consistent 
Make the style of the comment block for the Software Reset Clearing
Register offsets consistent with the comment blocks for the other
register offsets.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/97dde75fe3ff27b9639c59a43cddbd9d5c405d0c.1620119700.git.geert+renesas@glider.be
 2021-05-27 15:27:16 +02:00
Geert Uytterhoeven
682b108ba5 clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions 
The Realtime Module Stop Control Register definitions (RMSTPCR(i)) are
incorrect for i >= 8 on R-Car Gen2 and Gen3.

As these are unused, and not planned to be used, just like the
corresponding Modem Module Stop Control Register definitions (MMSTPCR())
on R-Mobile APE6 (they are intended for the software running on the
Real-Time and Modem CPU cores), they can just be removed.

Reported-by: Hai Nguyen Pham <hai.pham.ud@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/2d8bc4d9806b419ebb06030d2f31b2ea1e59b1d6.1620119700.git.geert+renesas@glider.be
 2021-05-27 15:25:00 +02:00
Geert Uytterhoeven
6bd913f54f clk: renesas: r9a06g032: Switch to .determine_rate() 
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the divider clocks on RZ/N1 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

Note that range checking is not yet implemented.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7a384d02b85cdaac4a0e2b357582c8244b9a6f98.1617282116.git.geert+renesas@glider.be
 2021-05-11 10:00:40 +02:00
Geert Uytterhoeven
02c69593e6 clk: renesas: div6: Implement range checking 
Consider the minimum and maximum clock rates imposed by clock users when
calculating the most appropriate clock rate in the .determine_rate()
callback.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35ceb262c71f1b2e9864a39bde9dafd78b2981f4.1617281699.git.geert+renesas@glider.be
 2021-05-11 09:58:13 +02:00
Geert Uytterhoeven
1c924fc679 clk: renesas: div6: Consider all parents for requested rate 
Currently the .determine_rate() callback considers only the current
parent clock, limiting the range of achievable clock rates on DIV6
clocks with multiple parents, as found on SH/R-Mobile SoCs.

Extend the callback to consider all available parent clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/60e639692b462f99e0b6ab868c3675b3d97dbdb0.1617281699.git.geert+renesas@glider.be
 2021-05-11 09:58:13 +02:00
Geert Uytterhoeven
c9d1b58b27 clk: renesas: div6: Switch to .determine_rate() 
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the DIV6 clocks on SH/R-Mobile and R-Car
SoCs from the old .round_rate() callback to the newer .determine_rate()
callback, which does not suffer from this limitation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7fd8c45cd8bf5c6d928ca69c8b669be35b93de09.1617281699.git.geert+renesas@glider.be
 2021-05-11 09:58:13 +02:00
Geert Uytterhoeven
23b04c84e2 clk: renesas: div6: Simplify src mask handling 
Simplify the handling of the register bits to select the parent clock,
by storing a bitmask instead of separate shift and width values.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5f05a5110d222ce5a113e683fe2aa726f4100b73.1617281699.git.geert+renesas@glider.be
 2021-05-11 09:58:13 +02:00
Geert Uytterhoeven
6c7bc7dbcc clk: renesas: div6: Use clamp() instead of clamp_t() 
As "div" is already "unsigned int", adding "U" suffixes to the constants
"1" and "64" allows us to replace the call to clamp_t() by a call to
clamp().  This removes hidden casts, and thus helps the compiler doing a
better job at type-checking.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2670c1e3c82a245666578cbbd1fb20d37932fd8e.1617281699.git.geert+renesas@glider.be
 2021-05-11 09:58:12 +02:00
Dinghao Liu
a20a40a8bb clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe() 
The error handling paths after pm_runtime_get_sync() have no refcount
decrement, which leads to refcount leak.

Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Link: https://lore.kernel.org/r/20210415073338.22287-1-dinghao.liu@zju.edu.cn
[geert: Remove now unused variable priv]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-05-11 09:57:07 +02:00
Niklas Söderlund
16927401d9 clk: renesas: r8a779a0: Add ISPCS clocks 
Add support for the ISPCS clocks on R-Car V3U.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210329223220.1139211-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-05-11 09:57:07 +02:00
Geert Uytterhoeven
3a0e848458 clk: renesas: rcar-gen3: Add boost support to Z clocks 
Add support for switching the Z and Z2 clocks between normal and boost
modes, by requesting clock rate changes to parent PLLs.

Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-8-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
3f70795636 clk: renesas: rcar-gen3: Add custom clock for PLLs 
Currently the PLLs are modeled as fixed factor clocks, based on initial
settings.  However, enabling CPU boost clock rates requires increasing
the PLL clock rates.

Add a custom clock driver to model the PLL clocks.  This will allow the
Z (CPU) clock driver to request changing the PLL clock rate.

Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-7-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
50086045bd clk: renesas: rcar-gen3: Increase Z clock accuracy 
Improve accuracy in the .determine_rate() callback for Z and Z2 clocks
by using rounded divisions.  This is similar to the calculation of rates
and multipliers in the .recalc_rate() resp. set_rate() callbacks.

Sample impact for a few requested clock rates:
  - R-Car H3:
      - Z 500 MHz:	468 MHz => 515 MHz
      - Z2 1000 MHz:	973 MHz => 1011 MHz
  - R-Car M3-W:
      - Z 500 MHz:	422 MHz => 516 MHz
      - Z2 800 MHz:	750 MHz => 788 MHz

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-6-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
67a1b9b651 clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/ 
Fix grammar in comments for cpg_z_clk_set_rate().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-5-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
c141897caa clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate() 
Due to the clamping of mult, "(32 - mult) << __ffs(zclk->mask)" can
never exceed the mask.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-4-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
58effcd350 clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32 
cpg_z_clk.mask contains a mask for a 32-bit register.
Hence its size can be reduced from unsigned long to u32.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-3-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
192c344e7c clk: renesas: rcar-gen3: Update Z clock rate formula in comments 
The fixed divider in the calculation of the Z and Z2 clock rates was
generalized from a hardcoded value of two to a parameterized value, but
the comments were not updated accordingly.

Fixes: 20cc05ba04 ("clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-2-geert+renesas@glider.be
 2021-05-11 09:57:06 +02:00
Geert Uytterhoeven
f2fb4fe623 clk: renesas: Zero init clk_init_data 
As clk_core_populate_parent_map() checks clk_init_data.num_parents
first, and checks clk_init_data.parent_names[] before
clk_init_data.parent_data[] and clk_init_data.parent_hws[], leaving the
latter uninitialized doesn't do harm for now.  However, it is better to
play it safe, and initialize all clk_init_data structures to zeroes, to
avoid any current and future members containing uninitialized data.

Remove a few explicit zero initializers, which are now superfluous.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210326105434.1574796-1-geert+renesas@glider.be
 2021-03-30 09:58:27 +02:00
Bhaskar Chowdhury
dbb397ccc6 clk: renesas: Couple of spelling fixes 
s/suposed/supposed/
s/concurent/concurrent/

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20210321075813.9471-1-unixbhaskar@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-24 10:41:50 +01:00
Wolfram Sang
0eedab655e clk: renesas: r8a779a0: Add CMT clocks 
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210311092939.3129-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-12 09:23:24 +01:00
Niklas Söderlund
95acd758fe clk: renesas: r8a7795: Add TMU clocks 
Add TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210310104554.3281912-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-12 09:22:46 +01:00
Niklas Söderlund
c66424ea75 clk: renesas: r8a779a0: Add TSC clock 
Implement support for the TSC clock on V3U.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210309165538.2682268-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-10 10:49:20 +01:00
Wolfram Sang
c52f4f839a clk: renesas: r8a779a0: Add TMU clocks 
Also add CL16MCK source clock for TMU0.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210305143259.12622-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-10 10:48:57 +01:00
Fabrizio Castro
429db43e84 clk: renesas: r8a77965: Add DAB clock 
This patch adds the DAB clock to the R8A77965 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20210225225147.29920-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-08 10:30:02 +01:00
Fabrizio Castro
12a7f8ce82 clk: renesas: r8a77990: Add DAB clock 
This patch adds the DAB clock to the R8A77990 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20210225225147.29920-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-08 10:30:02 +01:00
Lee Jones
24ece96554 clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation 
Fixes the following W=1 kernel build warning(s):

 drivers/clk/renesas/renesas-cpg-mssr.c:168: warning: Function parameter or member 'smstpcr_saved' not described in 'cpg_mssr_priv'

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-12-lee.jones@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-28 09:45:56 +01:00
Wolfram Sang
c5e91ba25a clk: renesas: r8a779a0: Add RAVB clocks 
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121100619.5653-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-25 09:46:22 +01:00
Wolfram Sang
6893a77279 clk: renesas: r8a779a0: Add I2C clocks 
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121095420.5023-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-25 09:46:22 +01:00
Geert Uytterhoeven
2b6587288a clk: renesas: r8a779a0: Add SYS-DMAC clocks 
Add the module clocks used by the Direct Memory Access Controller for
System (SYS-DMAC) instances on the Renesas R-Car V3U (r8a779a0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210107180109.1946475-1-geert+renesas@glider.be
 2021-01-12 12:35:13 +01:00
Wolfram Sang
792501727c clk: renesas: r8a779a0: Add SDHI support 
We use the shiny new CPG library for that.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-12 12:35:13 +01:00
Wolfram Sang
8bb67d8734 clk: renesas: rcar-gen3: Factor out CPG library 
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock handling and hook it to the generic Gen3 CPG driver so we
have an equal state. V3U will make use of it in the next patch then.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-12 12:35:13 +01:00