The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.
Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.
Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Christophe Roullier <christophe.roullier@foss.st.com>
Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Boolean properties in DT are present or not present and don't take a value.
A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't
matter.
It may have been intended that 0 values are false, but there is no change
in behavior with this patch.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/Yk3m92Sj26/v1mLG@robh.at.kernel.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Boolean properties in DT are present or not present and don't take a value.
A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't
matter.
It may have been intended that 0 values are false, but there is no change
in behavior with this patch.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/Yk3mR5yae3gCkKhp@robh.at.kernel.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Boolean properties in DT are present or not present and don't take a value.
A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't
matter.
It may have been intended that 0 values are false, but there is no change
in behavior with this patch.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/Yk3leykDEKGBN8rk@robh.at.kernel.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM Vexpress fixes for 5.18
Couple of fixes to address negative array index access and kernel-doc
build warnings.
* tag 'vexpress-fixes-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: vexpress/spc: Fix all the kernel-doc build warnings
ARM: vexpress/spc: Fix kernel-doc build warning for ve_spc_cpu_in_wfi
ARM: vexpress/spc: Avoid negative array index when !SMP
Link: https://lore.kernel.org/r/20220407110828.1436206-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There are more kernel-doc build warnings as below than the ones reported
by kernel test robot recently for this file.
| arch/arm/mach-vexpress/spc.c:125: warning: missing initial short description on line:
| * ve_spc_global_wakeup_irq()
| arch/arm/mach-vexpress/spc.c:131: warning: contents before sections
| arch/arm/mach-vexpress/spc.c:148: warning: missing initial short description on line:
| * ve_spc_cpu_wakeup_irq()
| arch/arm/mach-vexpress/spc.c:154: warning: contents before sections
| arch/arm/mach-vexpress/spc.c:203: warning: missing initial short description on line:
| * ve_spc_powerdown()
| arch/arm/mach-vexpress/spc.c:209: warning: contents before sections
| arch/arm/mach-vexpress/spc.c:231: warning: missing initial short description on line:
| * ve_spc_cpu_in_wfi()
| 7 warnings
Fix all these warnings.
Link: https://lore.kernel.org/r/20220404130207.1162445-2-sudeep.holla@arm.com
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
As a final bit of preparation for converting to ARCH_MULTIPLATFORM,
change the interrupt handling for s3c24xx to use sparse IRQs.
Since the number of possible interrupts is already fixed and relatively
small per chip, just make it use all legacy interrupts preallocated
using the .nr_irqs field in the machine descriptor, rather than actually
allocating domains on the fly.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
BAST is the one machine that theoretically supports unmodified ISA
drivers for hardware on its PC/104 connector, using a custom version of
the inb()/outb() and inw()/outw() macros.
This is incompatible with the generic version used in asm/io.h, and
can't easily be used in a multiplatform kernel.
Removing the special case for 16-bit I/O port access on BAST gets us
closer to multiplatform, at the expense of any PC/104 users with 16-bit
cards having to either use an older kernel or modify their ISA drivers
to manually ioremap() the area and use readw()/write() in place of
inw()/outw(). Either way is probably ok, given that there is a
recurring discussion about dropping s3c24xx altogether, and many
traditional ISA drivers are already gone.
Machines other than BAST already have no support for ISA drivers, though a
couple of them do map one of the external chip-selects into the ISA port
range, using the same address for 8-bit and 16-bit I/O. It is unlikely
that anything actually uses this mapping, but it's also easy to keep
this working by mapping it to the normal platform-independent PCI I/O
base that is otherwise unused on s3c24xx.
The mach/map-base.h file is no longer referenced in global headers and
can be moved into the platform directory.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Most LicheePi Nano boards come with soldered SPI flash, so enable SPI0
in the .dts and describe the flash chip. There is evidence of different
flash chips used, also of boards with no flash chip soldered, but the
Winbond 16MiB model is the most common, so use that for the compatible
string. The actual flash chip model will be auto-detected at runtime
anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-13-andre.przywara@arm.com
The F1C100 series contains two SPI controllers, and many boards use SPI0
for a SPI flash, as the BROM is able to boot from that.
Describe the two controllers in the SoC .dtsi, and also add the PortC
pins for SPI0, since this is where BROM looks at when trying to boot
from the commonly used SPI flash.
The SPI controller seems to be the same as in the H3 chips, but it lacks
a separate mod clock. The manual says it's connected to AHB directly.
We don't export that AHB clock directly, but can use the AHB *gate* clock
as a clock source, since the SPI driver is not supposed to change the AHB
frequency anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-12-andre.przywara@arm.com
The F1C100 series contains two MMC controllers, where the first one is
typically connected to an (micro)SD card slot (as this is the one the
BROM is able to boot from).
Describe the two controllers in the SoC .dtsi.
We also add the pinctrl description for MMC0, since this is the only
pin set supporting that function anyway, and SD cards are very common
across boards.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-9-andre.przywara@arm.com
The F1C100 series of SoCs actually have their watchdog IP being
compatible with the newer Allwinner generation, not the older one.
The currently described sun4i-a10-wdt actually does not work, neither
the watchdog functionality (just never fires), nor the reset part
(reboot hangs).
Replace the compatible string with the one used by the newer generation.
Verified to work with both the watchdog and reboot functionality on a
LicheePi Nano.
Also add the missing interrupt line and clock source, to make it binding
compliant.
Fixes: 4ba16d17ef ("ARM: dts: suniv: add initial DTSI file for F1C100s")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-4-andre.przywara@arm.com
The CONFIG_TEGRA_VDE has been deprecated and replaced with the new V4L
options after de-staging of the tegra-vde driver. Update the config entry.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of changing default pwm-cells property, use the default
"#pwm-cells = <3>" and add the third option.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This is effectively a revert of the temporary disablement
patch. Battery charging now works!
We also enable static battery data for the Samsung SDI
batteries as used by the U8500 Samsung phones.
Cc: Lee Jones <lee.jones@linaro.org>
Fixes: a1149ae975 ("ARM: ux500: Disable Power Supply and Battery Management by default")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This activates display drivers that give console on the
different U8500 mobile phones, the GNSS subsystem and the
SIRF GNSS driver so we can manage the GPS chips, the regulator
LEDs as used in some phones and one more IIO light sensor driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The gpio1 0 pin is controlling CAN termination, not USB H1 VBUS. So,
remove wrong regulator and assign this gpio to new DT CAN termination
property.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
countedX lines have different board names (YACO_x). And REV_ and BOARD_ pins
have multiple functions. So, use names exposed to the OS.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
backlight_led is the dimmable backlight for the rubber border on the case. It
is also used to highlight the power- and some other buttons.
MX6QDL_PAD_SD4_DAT1__PWM3_OUT is also assigned as output for pwm3. Since
we need pwm3 for the backlight, we're forced to disable user space hardware
revision detection. The bootloader will have to supply this information
(i.e. through device tree).
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
We have two backlight sources on this boards. Use more specific name for
the LCD backlight to see the difference.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This just updates the U8500 defconfig to reflect what has
happened in the Kconfig: DRM_PANEL_SONY_ACX424AKP is now
handled by DRM_PANEL_NOVATEK_NT35560, all ST sensors have
SPI version drivers that we don't use, and some debug
options moved around.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The proximity sensor on the Codina is actually an
Amstaos TMD2672, not Mouser, so alter the DTS to reflect this.
Tested successfully with the IIO driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The et1macaddr NVRAM variable contains a MAC address for gmac1 on Asus
RT-AC88U. Add NVMEM cell for it and reference it in the gmac1 node.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
