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24009 Commits

Author SHA1 Message Date
Rob Herring
3891222d88 ARM: dts: at91: Fix boolean properties with values 
Boolean properties in DT are present or not present and don't take a value.
A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't
matter.

It may have been intended that 0 values are false, but there is no change
in behavior with this patch.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/Yk3leykDEKGBN8rk@robh.at.kernel.org
 2022-04-13 18:42:50 +02:00
Krzysztof Kozlowski
4a6471e650 ARM: dts: at91: use generic node name for dataflash 
The node names should be generic, so use "flash" for dataflash nodes and
for cfi-flash.

Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220412105013.249793-1-krzysztof.kozlowski@linaro.org
 2022-04-13 18:42:50 +02:00
Krzysztof Kozlowski
e5628110bb ARM: dts: at91: align SPI NOR node name with dtschema 
The node names should be generic and SPI NOR dtschema expects "flash".

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220407143223.295344-1-krzysztof.kozlowski@linaro.org
 2022-04-13 18:42:50 +02:00
Tudor Ambarus
68a9345536 ARM: dts: at91: sama7g5ek: Align the impedance of the QSPI0's HSIO and PCB lines 
The impedance of the QSPI PCB lines on the sama7g5ek is 50 Ohms.
Align the output impedance of the QSPI0 HSIOs by setting a medium drive
strength which corresponds to an impedance of 56 Ohms when VDD is in the
3.0V - 3.6V range. The high drive strength setting corresponds to an
output impedance of 42 Ohms on the QSPI0 HSIOs.

Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220406130505.422042-1-tudor.ambarus@microchip.com
 2022-04-13 18:42:50 +02:00
Eugen Hristev
3f7ce6d709 ARM: dts: at91: sama7g5ek: enable pull-up on flexcom3 console lines 
Flexcom3 is used as board console serial. There are no pull-ups on these
lines on the board. This means that if a cable is not connected (that has
pull-ups included), stray characters could appear on the console as the
floating pins voltage levels are interpreted as incoming characters.
To avoid this problem, enable the internal pull-ups on these lines.

Fixes: 7540629e2f ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Cc: stable@vger.kernel.org # v5.15+
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220307113827.2419331-1-eugen.hristev@microchip.com
 2022-04-13 18:41:14 +02:00
Sergiu Moga
df96e96a8c ARM: dts: at91: sama7g5: Swap rx and tx for i2c nodes 
Swap `rx` and `tx` for the `dma-names` property of the `i2c` nodes
in order to maintain consistency across Microchip/Atmel SoC files.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220310114553.184763-2-sergiu.moga@microchip.com
 2022-04-13 18:35:49 +02:00
Wolfram Sang
cb97d48555 ARM: dts: rzg1: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220322095512.4707-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 13:43:03 +02:00
Wolfram Sang
2e4d5fd6f5 ARM: dts: rcar-gen2: Add interrupt properties to watchdog nodes 
Driver doesn't use it yet, but let's describe the HW properly.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220322095512.4707-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 13:43:03 +02:00
Rohit Agarwal
78254f3b7d ARM: dts: qcom: sdx65: Add support for TCSR Mutex 
Add TCSR Mutex node to support Qualcomm Hardware Mutex block
on SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-7-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:06 -05:00
Rohit Agarwal
98187f7b74 ARM: dts: qcom: sdx65: Enable ARM SMMU 
Add a node for the ARM SMMU found in the SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-6-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:05 -05:00
Rohit Agarwal
dc1a380fcb ARM: dts: qcom: sdx65: Add support for SDHCI controller 
Add devicetree support for SDHCI controller found in Qualcomm SDX65
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-4-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:05 -05:00
Rohit Agarwal
a30be44449 ARM: dts: qcom: sdx65: Add reserved memory nodes 
Add reserved memory nodes to the SDX65 dtsi as defined by
the memory map.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:04 -05:00
Krzysztof Kozlowski
43cdc159d2 ARM: dts: qcom: do not use underscore in node name 
Align RPM requests node with DT schema by using hyphen instead of
underscore.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[bjorn: Fixed up qcom-{apq8074,msm8974}-*.dts to match the qcom-msm8974.dtsi]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220401201035.189106-8-krzysztof.kozlowski@linaro.org
 2022-04-12 22:34:06 -05:00
Krzysztof Kozlowski
c19865df6b ARM: dts: qcom: msm8974-samsung-klte: move gpio-keys out of soc 
The GPIO keys are not part of SoC and they should be defined inside of
the root node.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220401201035.189106-6-krzysztof.kozlowski@linaro.org
 2022-04-12 22:29:41 -05:00
Krzysztof Kozlowski
d3eff0e174 ARM: dts: qcom: msm8974-lge-nexus5: move gpio-keys out of soc 
The GPIO keys are not part of SoC and they should be defined inside of
the root node.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220401201035.189106-5-krzysztof.kozlowski@linaro.org
 2022-04-12 22:29:40 -05:00
Rohit Agarwal
dc39466a73 ARM: dts: qcom: sdx65-mtp: Add regulator nodes 
Add the regulators found on SDX65 MTP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-7-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:29:40 -05:00
Rohit Agarwal
52fedb2f32 ARM: dts: qcom: sdx65: Add rpmpd node 
Add rpmpd node and opps for this node to the SDX65 dts.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:29:40 -05:00
Rohit Agarwal
1ebc5adc26 ARM: dts: qcom: sdx65-mtp: Add pmx65 pmic 
SDX65-mtp features PMX65 pmic, so include the dts as well.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-4-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:29:40 -05:00
Rohit Agarwal
73de2adfb2 ARM: dts: qcom: Add PMIC pmx65 dts 
Add DTS for PMIC PMX65 found in Qualcomm platforms.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-6-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:29:40 -05:00
Rohit Agarwal
26380f298b ARM: dts: qcom: sdx65-mtp: Add pmk8350b and pm8150b pmic 
SDX65-mtp features PMK8350b and PM8150B pmic, so include the dts as well

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-3-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:55:38 -05:00
Rohit Agarwal
324db76df1 ARM: dts: qcom: sdx65: Add spmi node 
Add SPMI node to SDX65 dtsi.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-2-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:55:37 -05:00
Ansuel Smith
a5ba119455 ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064 
Add syscon compatible required for tsens driver to correctly probe driver
and access the reg. Also add cxo and pxo tag and declare them as gcc clock
now requires them for the ipq8064 gcc driver that has now been modernized.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com
 2022-04-12 21:40:24 -05:00
Luca Weiss
d3236c598e ARM: dts: qcom: Add support for ASUS ZenWatch 2 
Add support for this smartwatch, based on Snapdragon 400 SoC.

Currently supported functionality:
* Internal storage
* USB
* Charger
* Power button
* Vibration motor
* Bluetooth
* Wifi

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226101939.1011551-2-luca@z3ntu.xyz
 2022-04-12 21:35:40 -05:00
Dmitry Baryshkov
6ffe07ba14 ARM: dts: qcom: msm8974: Drop flags for mdss irqs 
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.

Fixes: 5a9fc531f6 ("ARM: dts: msm8974: add display support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302225411.2456001-6-dmitry.baryshkov@linaro.org
 2022-04-12 21:34:35 -05:00
Howard Chiu
32e62d1bea ARM: dts: aspeed: Add video engine to g6 
This node was accidentally removed by commit 645afe73f9 ("ARM: dts:
aspeed: ast2600: Update XDMA engine node").

Fixes: 645afe73f9 ("ARM: dts: aspeed: ast2600: Update XDMA engine node")
Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>
Link: https://lore.kernel.org/r/SG2PR06MB2315C57600A0132FEF40F21EE61E9@SG2PR06MB2315.apcprd06.prod.outlook.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-04-13 11:53:53 +09:30
Zev Weiss
badcffaf87 ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name 
This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
correction from ASRock Rack its name now reflects its actual
functionality (POST_COMPLETE_N).

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: a9a3d60b93 ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220331022425.28606-2-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-04-13 11:53:52 +09:30
Zev Weiss
dd7c738684 ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values 
With this property set the sensor readings from these devices can now
be calibrated properly.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: a9a3d60b93 ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220331022425.28606-1-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-04-13 11:53:52 +09:30
Jae Hyun Yoo
890362d41b ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group 
Fix incorrect function mappings in pinctrl_qspi1_default and
pinctrl_qspi2_default since their function should be SPI1 and
SPI2 respectively.

Fixes: f510f04c8c ("ARM: dts: aspeed: Add AST2600 pinmux nodes")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220329173932.2588289-8-quic_jaehyoo@quicinc.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-04-13 11:53:52 +09:30
Johnny Huang
e194aff006 ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi 
Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode.
These pins can be used with dedicated FW SPI pins - FWSPICS0#,
FWSPICK, FWSPIMOSI and FWSPIMISO.

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220329173932.2588289-7-quic_jaehyoo@quicinc.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-04-13 11:53:52 +09:30
Jae Hyun Yoo
efddaa397c ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi 
FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove
FWQSPID group in pinctrl dtsi. These pins must be used with the
FWSPI pins that are dedicated for boot SPI interface which provides
same 3.3v logic level.

Fixes: 2f6edb6bcb ("ARM: dts: aspeed: Fix AST2600 quad spi group")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220329173932.2588289-2-quic_jaehyoo@quicinc.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-04-13 11:53:52 +09:30
Rohit Agarwal
ce91bc005e ARM: dts: qcom: sdx65: Add support for APCS block 
The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:22:34 -05:00
Rohit Agarwal
02c5553523 ARM: dts: qcom: sdx65: Add support for A7 PLL clock 
On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:22:26 -05:00
Rayyan Ansari
c20aa951ee ARM: dts: qcom: pm8226: Add VADC node 
Add a node for the voltage ADC (VADC) found in PM8226.

Signed-off-by: Rayyan Ansari <rayyan@ansari.sh>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220209163841.7360-1-rayyan@ansari.sh
 2022-04-12 21:20:06 -05:00
Kuldeep Singh
7224013d4b ARM: dts: qcom: ipq8064: User generic node name for DMA 
Qcom BAM DT spec expects generic DMA controller node name as
"dma-controller" to enable validations.

Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410175056.79330-6-singh.kuldeep87k@gmail.com
 2022-04-12 19:36:17 -05:00
Kuldeep Singh
a86efc02b3 ARM: dts: qcom: ipq4019: User generic node name for DMA 
Qcom BAM DT spec expects generic DMA controller node name as
"dma-controller" to enable validations.

Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410175056.79330-5-singh.kuldeep87k@gmail.com
 2022-04-12 19:36:17 -05:00
Kuldeep Singh
fb1bdb7e78 ARM: dts: qcom: apq8064: User generic node name for DMA 
Qcom BAM DT spec expects generic DMA controller node name as
"dma-controller" to enable validations.

Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410175056.79330-2-singh.kuldeep87k@gmail.com
 2022-04-12 14:24:40 -05:00
Kuldeep Singh
fbf64afd16 ARM: dts: qcom: mdm9615: User generic node name for DMA 
Qcom BAM DT spec expects generic DMA controller node name as
"dma-controller" to enable validations.

Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220410175056.79330-3-singh.kuldeep87k@gmail.com
 2022-04-12 14:24:26 -05:00
Tony Lindgren
8d2453d9a3 ARM: dts: dra7: Fix suspend warning for vpe powerdomain 
We currently are getting the following warning after a system suspend:

Powerdomain (vpe_pwrdm) didn't enter target state 0

Looks like this is because the STANDBYMODE bit for SMART_IDLE should
not be used. The TRM "Table 12-348. VPE_SYSCONFIG" says that the value
for SMART_IDLE is "0x2: Same behavior as bit-field value of 0x1". But
if the SMART_IDLE value is used, PM_VPE_PWRSTST LASTPOWERSTATEENTERED
bits always show value of 3.

Let's fix the issue by dropping SMART_IDLE for vpe. And let's also add
the missing the powerdomain for vpe.

Fixes: 1a20951605 ("ARM: dts: dra7: Add ti-sysc node for VPE")
Cc: Benoit Parrot <bparrot@ti.com>
Reported-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
 2022-04-12 12:55:47 +03:00
Jack Matthews
09e3dac420 ARM: dts: qcom: pm8226: add node for RTC 
Add a node for PM8226's real time clock.

Signed-off-by: Jack Matthews <jm5112356@gmail.com>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220209165742.652890-1-jm5112356@gmail.com
 2022-04-11 21:42:31 -05:00
Krzysztof Kozlowski
e4cbe44ec6 ARM: dts: qcom: msm8660: disable GSBI8 
The GSBI8 child node (I2C controller) is disabled, so as parent GSBI
node should be the same.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-6-krzysztof.kozlowski@linaro.org
 2022-04-11 21:38:03 -05:00
Krzysztof Kozlowski
bec8191807 ARM: dts: qcom: ipq4019: align clocks in I2C with DT schema 
The DT schema expects clocks core-iface order.  No functional change.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-5-krzysztof.kozlowski@linaro.org
 2022-04-11 21:37:53 -05:00
Krzysztof Kozlowski
17c15a4ccf ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema 
The DT schema expects dma channels in tx-rx order.  No functional
change.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-4-krzysztof.kozlowski@linaro.org
 2022-04-11 21:37:45 -05:00
Krzysztof Kozlowski
0f375d3aa6 ARM: dts: qcom: rename WCNSS child name to bluetooth 
The "bluetooth" is more popular and more descriptive than "bt", for a
Bluetooth device.  The WCNSS DT schema will expect such naming.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405065752.27389-1-krzysztof.kozlowski@linaro.org
 2022-04-11 21:35:57 -05:00
Krzysztof Kozlowski
50769f32af ARM: dts: qcom: align SPI NOR node name with dtschema 
The node names should be generic and SPI NOR dtschema expects "flash".

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220407143112.294930-1-krzysztof.kozlowski@linaro.org
 2022-04-11 21:28:24 -05:00
Tony Lindgren
c7d7d0ce29 ARM: dts: Drop custom clkctrl compatible and update omap5 l4per 
We can now use the clock-output-names and don't need custom compatible
values for each clkctrl instance. And we can use a generic name also for
the clock manager instance.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Message-Id: <20220204084339.12341-5-tony@atomide.com>
 2022-04-11 16:03:35 +03:00
Tony Lindgren
7359c0aee7 ARM: dts: Add clock-output-names for omap5 
To stop using the non-standard node name based clock naming, let's
first add the clock-output-names property. This allows us to stop using
the internal legacy clock naming and unify the naming for the TI SoCs in
the following patches.

Note that we must wait on fixing the node naming issues until after the
internal clock names have been updated to avoid adding name translation
unnecessarily.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Message-Id: <20220204084339.12341-4-tony@atomide.com>
 2022-04-11 16:03:34 +03:00
Tony Lindgren
0752506039 ARM: dts: Drop custom clkctrl compatible and update omap4 l4per 
We can now use the clock-output-names and don't need custom compatible
values for each clkctrl instance. And we can use a generic name also for
the clock manager instance.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Message-Id: <20220204084339.12341-3-tony@atomide.com>
 2022-04-11 16:03:34 +03:00
Tony Lindgren
da541a6c19 ARM: dts: Add clock-output-names for omap4 
To stop using the non-standard node name based clock naming, let's
first add the clock-output-names property. This allows us to stop using
the internal legacy clock naming and unify the naming for the TI SoCs in
the following patches.

Note that we must wait on fixing the node naming issues until after the
internal clock names have been updated to avoid adding name translation
unnecessarily.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Message-Id: <20220204084339.12341-2-tony@atomide.com>
 2022-04-11 16:03:34 +03:00
Tony Lindgren
f8ca5f5ae5 ARM: dts: Use clock-output-names for am4 
With the TI clocks supporting the use of clock-output-names devicetree
property, we no longer need to use non-standard node names for clocks.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Message-Id: <20220204081529.57694-1-tony@atomide.com>
 2022-04-11 16:03:33 +03:00
Tony Lindgren
e4920169e7 ARM: dts: Use clock-output-names for dra7 
With the TI clocks supporting the use of clock-output-names devicetree
property, we no longer need to use non-standard node names for clocks.

Depends-on: 31aa7056bb ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl")
Depends-on: 9206a3af4f ("clk: ti: Move dra7 clock devices out of the legacy section")
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Message-Id: <20220204080842.40673-1-tony@atomide.com>
 2022-04-11 16:03:33 +03:00