Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c:50:1: warning: no previous prototype for ‘tu102_mc_intr_unarm’ [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c:62:1: warning: no previous prototype for ‘tu102_mc_intr_rearm’ [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c:74:1: warning: no previous prototype for ‘tu102_mc_intr_mask’ [-Wmissing-prototypes]
Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Alistair Popple <apopple@nvidia.com>
Cc: dri-devel@lists.freedesktop.org
Cc: nouveau@lists.freedesktop.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20210602143300.2330146-16-lee.jones@linaro.org
This is no longer needed now that tu102_mc_intr_stat has been updated to
look at the correct top-level interrupt bits.
Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Turing reports MMU fault interrupts via new top level interrupt
registers. The old PMC MMU interrupt vector is not used by the HW. This
means we can remap the new top-level MMU interrupt to the exisiting PMC
MMU bit which simplifies the implementation until all interrupts are
moved over to using the new top level registers.
Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
