Change to the extended cfi table parsing for Intel NOR flash that uses
the info in the extended table to 'walk' the table rather than using
hard coding for various primary extended query table version numbers.
From: Jared Hulbert <jaredeh@gmail.com>
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
While this might be useful for all supported flash types, it is mandatory
for proper JFFS2 support with Sibley flash.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This updates the Primary Vendor-Specific Extended Query parsing to
version 1.4 in order to get the information about the Configurable
Programming Mode regions implemented in the Sibley flash, as well as
selecting the appropriate write command code.
This flash does not behave like traditional NOR flash when writing data.
While mtdblock should just work, further changes are needed for JFFS2 use.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This includes improved error handling/reporting plus some other
message cleanups.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Modify Amd/Fujitsu CFI NOR flash primary vendor extension table revision
check to recognize version 1.4. Verified the existing driver can
handle version 1.4 chips without additional info from 1.4 extended table.
Move the primary vendor extension table revision check from common file
to the 3 CFI chip driver files, since the data structures and revisions
handled by those data structures are specific to the chip driver.
Modify the error message printed when the revision is unknown to be a
KERN_ERR instead of WARNING since this will cause mtd to ignore the chip.
Signed-off-by: Todd Poynor <tpoynor@mvista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This reworks the XIP locking to make sure no lock primitive is ever
called from XIP disabled paths even if in theory they should not
cause any reschedule. Relying on the current spinlock implementation
is rather fragile and not especially clean from an abstraction pov.
The recent RT work makes it even more obvious.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
to make sure the flash is in array mode whenever we're about to
reboot. This is especially useful to allow "soft" reboot to work
which consists of branching back into the bootloader.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Skip jiffy delay after each block lock/unlock for Intel CFI flash
with the "Instant Individual Block Locking" feature bit set.
Signed-off-by: Todd Poynor <tpoynor@mvista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
oldstate has to be reset to FL_READY after sync completion.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The change makes the code endianess aware and replaces the bogus
nested loop to or the status flags together.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This enables support for reading, writing and locking so called
"Protection Registers" present on some flash chips.
A subset of them are pre-programmed at the factory with a
unique set of values. The rest is user-programmable.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
