The properties have been commented out to prevent a regression a while
ago. The first regression should be resolved by commit 44af792731
("spi: Map SPI OF client IRQ at probe time").
The second regression is probably addressed by commit 494fd7b7ad
("PM / core: fix deferred probe breaking suspend resume order") and/or
maybe others. Readd the gpio-ranges properties to see whether
regressions still get reported.
This reverts commit 4f1d841475 ("ARM: tegra: Comment out gpio-ranges
properties").
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: drop redundant gpio-ranges from Ouya DTS file]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Move the default state pinmux definition into the pinmux node. There's
no need for the indirection via the phandle.
Note that the phandle indirection is kept for the EMC operating
performance point tables because they reference nodes that are defined
in an external file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Ouya board specifies the #reset-cells property for the GPIO
controller. Since the GPIO controller doesn't provide reset controls
this is not needed, so they can be dropped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement. Reorganize CPU and EMC OPP table device-tree nodes.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When the Tegra High-Speed UART is used instead of the regular UART, the
reg-shift property is implied from the compatible string and should not
be explicitly listed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The host-wakeup GPIO is now marked as deprecated in the broadcom-bluetooth
device-tree binding, it's replaced with the host-wakeup interrupt. Update
Tegra device-trees to the recent version of the Bluetooth binding.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The TEMP_ALERT pin of LM90 temperature sensor is connected to Tegra SoC.
Add interrupt property to the temperature sensor and enable it in pinmux,
for completeness.
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The ACTMON module monitors activity of memory clients and then devfreq
driver makes decisions about a required memory frequency based on info
from ACTMON. Add ACTMON device to the thermal zone of Ouya in order to
use it as a cooling device which throttles memory freq on overheat.
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Specify TPS65911 as wakeup source on Tegra devices in order to allow
its RTC to wake up system from suspend by default instead of requiring
wakeup to be enabled manually via sysfs.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
If CPU0 is unplugged the cooling device can not rebind to CPU1. And if
CPU0 is plugged in again, the cooling device may fail to initialize.
If the CPUs are mapped with the physical CPU0 to Linux numbering
CPU1, the cooling device mapping will fail.
Hence specify all CPU cores as a cooling devices in the device-tree.
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Ouya fails to detect the eMMC module when booted via certain bootloaders.
Fastboot and hard-kexec bootloaders fail while u-boot does not. It was
discovered that the issue manifests if the sdmmc4 alternate configuration
clock pin is input disabled.
Ouya uses sdmmc4 in the primary pin configuration. It is unknown why this
occurs, though it is likely related to other eMMC limitations experienced
on Ouya.
For now, fix it by enabling input on cam_mclk_pcc0.
Fixes: d7195ac5c9 ("ARM: tegra: Add device-tree for Ouya")
Reported-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add EMC OPP tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Update board device-trees by removing unsupported EMC OPPs.
Note that ACTMON watches all memory interconnect paths, but we use a
single CPU-READ interconnect path for driving memory bandwidth, for
simplicity.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Ouya was the sole device produced by Ouya Inc in 2013.
It was a game console originally running Android 5 on top of Linux 3.1.10.
This patch adds the device tree supporting the Ouya.
It has been tested on the original variant with Samsung ram.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
