Leo Liu
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d6b0185b8d
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drm/amdgpu: set the LMI ctrl and reset earlier
So the LMI register will be programmed properly
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2020-07-01 01:59:10 -04:00 |
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Leo Liu
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07d8e891ff
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drm/amdgpu: fix the PSP front door loading VCN firmware
for the second instance with correct index
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2020-07-01 01:59:10 -04:00 |
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Leo Liu
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14765e9c22
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drm/amdgpu: change the offset for VCN FW cache window
The signed header is added
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2020-07-01 01:59:10 -04:00 |
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Leo Liu
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fedac0155a
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drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2)
This is for static powergating and clockgating
v2: fix registers (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2020-07-01 01:59:09 -04:00 |
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Leo Liu
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cf14826cdf
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drm/amdgpu: add VCN3.0 support for Sienna_Cichlid
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2020-07-01 01:59:09 -04:00 |
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