linux

Author SHA1 Message Date

Author	SHA1	Message	Date
Michael Ellerman	192b2e742c	selftests/powerpc: Skip tm-trap if transactional memory is not enabled Some processor revisions do not support transactional memory, and additionally kernel support can be disabled. In either case the tm-trap test should be skipped, otherwise it will fail with a SIGILL. Fixes: `a08082f8e4` ("powerpc/selftests: Check endianness on trap in TM") Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>	2018-02-26 13:18:25 +11:00
Gustavo Romero	a08082f8e4	powerpc/selftests: Check endianness on trap in TM Add a selftest to check if endianness is flipped inadvertently to BE (MSR.LE set to zero) on BE and LE machines when a trap is caught in transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP and MSR.VEC are zeroed (disabled). Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>	2018-01-22 05:48:37 +11:00

Michael Ellerman

192b2e742c

selftests/powerpc: Skip tm-trap if transactional memory is not enabled

Some processor revisions do not support transactional memory, and
additionally kernel support can be disabled. In either case the
tm-trap test should be skipped, otherwise it will fail with a SIGILL.

Fixes: a08082f8e4 ("powerpc/selftests: Check endianness on trap in TM")
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

2018-02-26 13:18:25 +11:00

Gustavo Romero

a08082f8e4

powerpc/selftests: Check endianness on trap in TM

Add a selftest to check if endianness is flipped inadvertently to BE
(MSR.LE set to zero) on BE and LE machines when a trap is caught in
transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP
and MSR.VEC are zeroed (disabled).

Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

2018-01-22 05:48:37 +11:00

2 Commits