Commit Graph

3 Commits

Author SHA1 Message Date
Max Filippov
a5944195d0 xtensa: implement initialize_cacheattr for MPU cores
Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-07 10:36:34 -07:00
Max Filippov
f7c34874f0 xtensa: add exclusive atomics support
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-07 10:36:31 -07:00
Max Filippov
8f8d5745bb xtensa: replace variant/core.h with asm/core.h
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-06 17:48:55 -07:00