Yifan Zhang
431d071286
drm/amdgpu/mes: only invalid/prime icache when finish loading both pipe MES FWs.
...
invalid/prime icahce operation takes effect both pipes cuconrrently,
therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be
set before prime icache. Otherwise MES hardware gets garbage data in
above regsters and causes page fault
[ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0)
[ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10
[ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3
[ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5)
[ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1
[ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1
[ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb
[ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1
[ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Reviewed-by: Tim Huang <Tim.Huang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-06-08 15:39:16 -04:00
Jack Xiao
7bd3114b1c
drm/amdgpu/gfx11: fix mes mqd settings
...
Use the correct Memory Queue Descriptor (MQD)
structure for GC 11.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-16 10:02:57 -04:00
Huang Rui
b0abae7d5d
drm/amdgpu: add GC v11.0.1 into mes v11
...
Add GC v11.0.1 support into mes v11.
Signed-off-by: Huang Rui <ray.huang@amd.com >
Reviewed-by: Xiaojian Du <Xiaojian.Du@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-06 10:36:14 -04:00
Flora Cui
32697fea3a
drm/amdgpu: add mes 11 firmware for mes 11.0.2
...
Define firmware for MES 11.0.2.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Flora Cui <flora.cui@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:52:37 -04:00
Alex Deucher
98bae89647
drm/amdgpu/gfx11: remove some register fields that no longer exist
...
Some copy paste leftovers for older asics. They were protected
by __BIG_ENDIAN, so we didn't notice them initially.
Reported-by: kernel test robot <lkp@intel.com >
Reviewed-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:33:08 -04:00
Jack Xiao
d81d75c999
drm/amdgpu/gfx11: enable kiq to map mes ring
...
Enable KIQ to map MES ring:
1). add MES queue mapping support in MAP_QUEUES packet.
2). use correct MQD settings for MES queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:55 -04:00
Jack Xiao
028c3fb37e
drm/amdgpu/mes11: initiate mes v11 support
...
Initiate mes v11 code base from mes v10, rename function
and register names.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:54 -04:00
