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196 Commits

Author SHA1 Message Date
Tao Zhou
4da6783908 drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish 
Per PMFW 59.7.0.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:02:48 -04:00
Tao Zhou
7dc2ef4e70 drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish(v2) 
Per PMFW 59.5.0.

v2: refine subject and commit message, fix typo

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:02:31 -04:00
Tao Zhou
4ccc957f15 drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish 
Update driver if version from 0x5 to 0x6 for dimgrey_cavefish, per PMFW 59.04.0.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:02:29 -04:00
Tao Zhou
e8afbddfa1 drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish 
Update driver if version from 0x4 to 0x5 for dimgrey_cavefish, per PMFW 59.02.0.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:02:09 -04:00
Tao Zhou
4ed032bd13 drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish 
Update driver if version according to PMFW with version 0x003B0100.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:01:51 -04:00
Tao Zhou
db1f8a8fb2 drm/amdgpu/swsmu: add smu support for dimgrey_cavefish(v2) 
Reuse sienna_cichlid pp table for dimgrey_cavefish.

v2: update related comment.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:01:07 -04:00
Tao Zhou
10e0d9ebb0 drm/amdgpu/swsmu: increase size for smu fw_name string 
A longer chip name needs more space.

v2: define macro for the length of smu fw name

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:01:02 -04:00
Alex Deucher
75145aab7a drm/amdgpu/swsmu: clean up a bunch of stale interfaces 
These were leftover from the initial implementation, but
never used.  Drop them.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Noticed-by: Ryan Taylor <ryan.taylor@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:51:04 -04:00
Gustavo A. R. Silva
89c785bb1a drm/amd/pm: Replace one-element array with flexible-array in struct phm_samu_clock_voltage_dependency_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_samu_clock_voltage_dependency_table, instead of a one-element array,
and use the struct_size() helper to calculate the size for the allocation.

Also, save some heap space as the original code is multiplying
table->numEntries by sizeof(struct phm_samu_clock_voltage_dependency_table)
when it should have been multiplied it by
sizeof(struct phm_samu_clock_voltage_dependency_record) instead.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c5d3a.ryM4GmZr3e0JeZy+%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:30 -04:00
Gustavo A. R. Silva
aa8d10a10f drm/amd/pm: Replace one-element array with flexible-array in struct phm_cac_leakage_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_cac_leakage_table, instead of a one-element array,
and use the struct_size() helper to calculate the size for the allocation.

Also, save some heap space as the original code is multiplying
table->ucNumEntries by sizeof(struct phm_cac_leakage_table) when it
should have been multiplied it by sizeof(struct phm_cac_leakage_record)
instead.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c5d38.iT%2FQTjN+659XUDo5%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:30 -04:00
Gustavo A. R. Silva
637f7576ec drm/amd/pm: Replace one-element array with flexible-array in struct phm_vce_clock_voltage_dependency_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_vce_clock_voltage_dependency_table, instead of a one-element array,
and use the struct_size() helper to calculate the size for the allocation.

Also, save some heap space as the original code is multiplying
table->numEntries by sizeof(struct phm_vce_clock_voltage_dependency_table)
when it should have multiplied it by sizeof(struct phm_vce_clock_voltage_dependency_record)
instead.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c5d35.pJToGs3H9khZK6ws%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Gustavo A. R. Silva
9526e431c5 drm/amd/pm: Replace one-element array with flexible-array in struct phm_phase_shedding_limits_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_phase_shedding_limits_table, instead of a one-element array,
and use the struct_size() helper to calculate the size for the allocation.

Also, save some heap space as the original code is multiplying
ptable->ucNumEntries by sizeof(struct phm_phase_shedding_limits_table)
when it should have multiplied it by sizeof(struct phm_phase_shedding_limits_record)
instead.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c5d36.6PStUZp2HRxAz7IM%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Gustavo A. R. Silva
0e319cfeb3 drm/amd/pm: Replace one-element array with flexible-array in struct phm_acp_clock_voltage_dependency_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_acp_clock_voltage_dependency_table, instead of a one-element
array, and use the struct_size() helper to calculate the size for the
allocation.

Also, save some heap space as the original code is multiplying
table->numEntries by sizeof(struct phm_acp_clock_voltage_dependency_table)
when it should have multiplied it by sizeof(phm_acp_clock_voltage_dependency_record)
instead.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c5d3c.TyfOhg%2FA6JycL6ZN%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Gustavo A. R. Silva
737123d67e drm/amd/pm: Replace one-element array with flexible-array in struct phm_uvd_clock_voltage_dependency_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_uvd_clock_voltage_dependency_table, instead of a one-element
array, and use the struct_size() helper to calculate the size for the
allocation.

Also, save some heap space as the original code is multiplying
table->numEntries by sizeof(struct phm_uvd_clock_voltage_dependency_table)
when it should have multiplied it by sizeof(phm_uvd_clock_voltage_dependency_record)
instead.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c433e.pXkC6KsN6HN%2FLdhj%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Gustavo A. R. Silva
e0af7d1110 drm/amd/pm: Replace one-element array with flexible-array in struct phm_clock_array 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_clock_array, instead of a one-element array, and use the
struct_size() helper to calculate the size for the allocation.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c433f.ZyMD+YUIVAwiHGVe%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Gustavo A. R. Silva
2b61065756 drm/amd/pm: Replace one-element array with flexible-array member in struct vi_dpm_table 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Use a flexible-array member in struct vi_dpm_table instead of a
one-element array.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c433c.TTk9rnA+F58kyDUy%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Gustavo A. R. Silva
23bdba959b drm/amd/pm: Replace one-element array with flexible-array member 
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct phm_clock_voltage_dependency_table, instead of a one-element
array, and use the struct_size() helper to calculate the size for the
allocation.

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Build-tested-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/lkml/5f7c295c.8iqp1Ifc6oiVDq%2F%2F%25lkp@intel.com/
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-09 14:43:29 -04:00
Xiaojian Du
8877965869 drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2) 
This patch is to add vangogh asic name in smu v11.

v2: drop smu firmware name (N/A for VG)

Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Xiaojian Du
e89616baf7 drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh 
This patch is to add smu v11.5 smc header for vangogh.

Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Xiaojian Du
b44694a111 drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2) 
This patch is to add smu v11.5 firmware header for vangogh

v2: squash in updates

Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Xiaojian Du
572083bd99 drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh 
This patch is to add smu v11.5 driver interface header for vangogh.

Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Xiaojian Du
f57d62a00a drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2) 
This patch is to add new smu messages and feature masks for vangogh.

v2: squash in updates and typo fixes

Signed-off-by: Xiaojian Du <xiaojian.du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Alex Deucher
234676d6db drm/amdgpu/swsmu: add interrupt work handler for smu11 parts 
We need to schedule the smu AC/DC interrupt ack to avoid
potentially sleeping if the smu message mutex is contended.

Fixes: e1188aacad ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts")
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-01 10:43:28 -04:00
Alex Deucher
1a8a763b21 drm/amdgpu/swsmu: add interrupt work function 
So we can schedule work from interrupts.  This might include
long tasks or things that could sleep.

Fixes: e1188aacad ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts")
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-01 10:43:10 -04:00
Xiaojian Du
12a6727dee drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU. 
This patch is to add one sysfs file -- "pp_od_clk_voltage" for
Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10.
This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can
be used to configure the min value and the max value for gfx clock limited in the
safe range.

Command guide:
echo "s level clock" > pp_od_clk_voltage
	s - adjust teh sclk level
	level - 0 or 1, "0" represents the min value, "1" represents the max value
	clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the
                OD_RANGE limits.
Example:
$ cat pp_od_clk_voltage
OD_SCLK:
0:        200Mhz
1:       1400Mhz
OD_RANGE:
SCLK:     200MHz       1400MHz

$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:        600Mhz
1:       1000Mhz
OD_RANGE:
SCLK:     200MHz       1400MHz

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-29 16:12:16 -04:00
Likun Gao
b362a18ada drm/amd/pm: update driver if file for sienna cichlid 
Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-22 17:37:38 -04:00
Evan Quan
911779e3fc drm/amd/pm: add Raven2 watermark WmType setting 
Which tells it's a normal pstate change or memory retraining.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:48:18 -04:00
Evan Quan
7b9c7e30ab drm/amd/pm: drop unnecessary wrappers around watermark setting 
The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15"
is totally unnecessary and can be dropped.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:48:00 -04:00
Evan Quan
38d11e0249 drm/amd/pm: drop unnecessary table existence and dpm enablement check 
Either this was already performed in parent API. Or the table is
confirmed to exist.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:47:33 -04:00
Evan Quan
bb7257b5a8 drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares(V2) 
And different workaround will be applied based on hybrid cdr bit.

V2: add pmfw version guard to make sure the new workaround applied only
    with pmfw >= 42.53.0

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:46:47 -04:00
Evan Quan
665945eb49 drm/amd/pm: implement a new umc cdr workaround 
By uploading dummy pstate tables.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:46:40 -04:00
Evan Quan
2379be2faf drm/amd/pm: allocate a new buffer for pstate dummy reading 
This dummy reading buffer will be used for the new Navi1x
UMC CDR workaround.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:46:34 -04:00
Evan Quan
82cac71c1b drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init 
That's where the uclk dpm get enabled and then the
uclk cdr workaround can be applied.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:46:20 -04:00
Evan Quan
4bdd4d25ed drm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2) 
So that ASIC specific actions can be added.

V2: better namings

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-17 17:45:57 -04:00
Jiansong Chen
9c1615be19 drm/amd/pm: update driver if version for navy_flounder 
It's in accordance with pmfw 65.8.0 for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-15 17:52:39 -04:00
Likun Gao
0e4b291bb7 drm/amd/pm: update driver if file for sienna cichlid 
Update drive if file for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-15 17:52:39 -04:00
Alex Deucher
9a7fd01384 drm/amdgpu/swsmu: add smu11 helper to get manual fan speed (v2) 
Will be used to fetch the fan speeds when manual fan mode is
set.

v2: squash in a Coverity fix from Colin Ian King

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-03 14:46:55 -04:00
Alex Deucher
8d6e65adc2 drm/amdgpu/swsmu: drop set_fan_speed_percent (v2) 
No longer needed as we can calculate it based on
the fan's max rpm.

v2: minor code rework

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-03 14:46:55 -04:00
Alex Deucher
eff6474260 drm/amdgpu/swsmu: drop get_fan_speed_percent (v2) 
No longer needed as we can calculate it based on
the fan's max rpm.

v2: rework code to avoid possible uninitialized
variable use.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-03 14:46:55 -04:00
Alex Deucher
337b57aecb drm/amdgpu/swsmu: add new callback for getting fan parameters 
To fetch the max rpm from pptable.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-03 14:46:54 -04:00
Evan Quan
5ce99853a6 drm/amd/pm: add SMU11 common deep sleep control interface 
Considering the same logic can be applied to Arcturus, Navi1X
and Sienna Cichlid.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-18 18:21:56 -04:00
Evan Quan
f0d51d20d9 drm/amd/pm: disable/enable deep sleep features on UMD pstate enter/exit 
Add deep sleep disablement/enablement on UMD pstate entering/exiting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-18 18:21:50 -04:00
Evan Quan
e988026fcf drm/amd/pm: add SMU11 common gfx ulv control interface 
Considering the same logic can be applied to Arcturus, Navi1X
and Sienna Cichlid.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-18 18:21:43 -04:00
Evan Quan
588a4d5c6a drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit 
Add gfx ulv disablement/enablement on UMD pstate entering/exiting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-18 18:21:35 -04:00
Jiansong Chen
b109f61e7f drm/amd/pm: update driver if version for navy_flounder 
It's in accordance with pmfw 65.7.0 for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-18 18:21:27 -04:00
Evan Quan
e098bc9612 drm/amd/pm: optimize the power related source code layout 
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on different ASICs. Hopefully all these can make power part
more friendly to play with.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-14 16:22:41 -04:00