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23 Commits

Author SHA1 Message Date
Jake Wang
e7414a1a18 drm/amd/display: Disable hdmistream and hdmichar clocks 
[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-10-19 17:20:28 -04:00
Zhan Liu
0ad53fe3ae drm/amdgpu: add cyan_skillfish asic header files 
This patch is to add cyan_skillfish asic header files.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Jun Lei <jun.lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-09-29 17:30:00 -04:00
Chun-Liang Chang
556a979d3c drm/amd/display: DMUB Outbound Interrupt Process-X86 
[Why]
dmub would notify x86 response time violation by GPINT_DATAOUT

[How]
1. Use GPINT_DATAOUT to trigger x86 interrupt
2. Register GPINT_DATAOUT interrupt handler.
3. Trigger ACR while GPINT_DATAOUT occurred.

Signed-off-by: Chun-Liang Chang <Chun-Liang.Chang@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-07-08 15:14:36 -04:00
Wesley Chalmers
a659f2fdf8 drm/amd/display: Add interface to get Calibrated Avg Level from FIFO 
[WHY]
Hardware has handed down a new sequence requiring the value of this
register be read from clk_mgr.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-06-15 17:25:41 -04:00
Aaron Liu
02680c23d7 drm/amdgpu: add yellow carp asic header files (v3) 
This patch is to add yellow carp asic header files.

v2: squash in updates (Alex)
v3: squash in DCN updates (Alex)

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-06-04 16:03:05 -04:00
Aurabindo Pillai
015b448985 drm/amd/display: Edit license info for beige goby DC files 
[How]
* Add MIT license to all new files as SPDX tag.
* Fix copyright year

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-05-19 22:42:04 -04:00
Aurabindo Pillai
8198ace7a0 drm/amd/display: Add register definitions for Beige Goby 
[Why&How]
Adds registers definitions required for Beige Goby initial support.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-05-19 22:41:55 -04:00
Tom St Denis
e49db37634 drm/amd/amdgpu: Add missing BASE_IDX to dcn register 
The register mmOTG1_OTG_BLANK_CONTROL was missing BASE_IDX value.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2021-03-05 15:11:32 -05:00
Bhawanpreet Lakha
9713158cb2 drm/amdgpu: Add and use seperate reg headers for dcn302 
Currently we are using dcn3 reg headers for dcn302. The offsets are
different between the two so they need seperate headers.

Add dcn302 header files and use these instead of dcn3 header

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-11-10 14:15:08 -05:00
Huang Rui
a5b2c10c05 drm/amdgpu: add vangogh asic header files (v2) 
This patch is to add vangogh asic header files.

v2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:14:02 -04:00
Lukas Bulwahn
5049a05269 drm/amd/display: remove unintended executable mode 
Besides the intended change, commit 4cc1178e16 ("drm/amdgpu: replace DRM
prefix with PCI device info for gfx/mmhub") also set the source files
mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode
644 to new mode 755.

Commit 241b2ec931 ("drm/amd/display: Add dcn30 Headers (v2)") added the
four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e.,
mode 755.

Set to the usual modes for source and headers files and clean up those
mistakes. No functional change.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-24 12:23:02 -04:00
Bhawanpreet Lakha
6fecfc8252 drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3 
This field is not defined for DCN3

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-17 14:09:27 -04:00
Jerry (Fangzhi) Zuo
241b2ec931 drm/amd/display: Add dcn30 Headers (v2) 
DCN 3.0 display controller registers

v2: squash in updates from Bhawan.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-06-03 13:51:56 -04:00
Rodrigo Siqueira
d1dcb05f0e drm/amd/include: Add OCSC registers 
Add registers for handling Post Gamma Color Blending (OCSC), which is
useful for conversion from RGB->YUV for HDMI.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-01-16 13:41:06 -05:00
Roman Li
6fdcba3271 drm/amdgpu: move dpcs headers to dpcs includes 
- create dpcs directory for dpcs asic_reg headers
- move dpcs21 reg headers from dcn to dpcs directory

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-12-18 16:09:06 -05:00
Bhawanpreet Lakha
ce6095267d drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs 
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-10-17 16:27:07 -04:00
Bhawanpreet Lakha
b593bce59b drm/amd/display: Add Renoir registers (v3) 
add registers for dcn, clk, and renoir ip offsets

v2: header cleanup (Alex)
v3: Add DPCS registers (Hersen)

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-29 15:52:32 -05:00
Charlene Liu
bb21290ff6 drm/amd/display: Create DWB resource for DCN2 
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-22 09:34:11 -05:00
Hawking Zhang
d6ad5023e8 drm/amdgpu: add DCN 2.0 register headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-20 15:54:23 -05:00
Leo Li
3b8cea6f64 drm/amd/include: Add HUBPREQ_DEBUG register offsets 
They will be used by DC when runing ASIC-specific HUBP initialization.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-04-23 17:27:08 -05:00
Harry Wentland
86993018d7 drm/amdgpu: Add CM_TEST_DEBUG regs for DCN 
We'd like to use them for reading DCN debug status.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:07:35 -05:00
Harry Wentland
d89746ec4f drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROL 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:21 -05:00
Feifei Xu
ad941f7a8b drm/amd/include:cleanup raven1 dcn header files. 
Cleanup asic_reg/raven1/DCN folder.Remove unused
dcn_1_0_default.h.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-12-06 12:48:23 -05:00