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207 Commits

Author SHA1 Message Date
Harry Wentland
86a66c4eb7 drm/amd/display: Move mi, ipp, xfm to plane_res 
find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.mi/\.plane_res.mi/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->mi/->plane_res.mi/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.ipp/\.plane_res.ipp/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->ipp/->plane_res.ipp/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.xfm/\.plane_res.xfm/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->xfm/->plane_res.xfm/g'

To clean up bad renames:

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.min/\.min/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.min/->min/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.mic/->mic/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.mis/\.mis/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.mid/->mid/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.mid/\.mid/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.mis/->mis/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.min/\.min/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.min/->min/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.mic/->mic/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.mis/\.mis/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.mid/->mid/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.mid/\.mid/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->plane_res\.mis/->mis/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.plane_res\.ipps/\.ipps/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/mpcc_cfg\.plane_res\.mi/mpcc_cfg\.mi/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/mi->plane_res\./mi->/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/cfg->plane_res\./cfg->/g'

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:16:07 -04:00
Harry Wentland
6702a9ac53 drm/amd/display: Move scl_data to plane_res 
find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/\.scl_data/\.plane_res.scl_data/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/->scl_data/->plane_res.scl_data/g'

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:16:06 -04:00
Harry Wentland
3be5262e35 drm/amd/display: Rename more dc_surface stuff to plane_state 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:16:04 -04:00
Andrey Grodzovsky
b701542d29 drm/amd/display: fix >340 Mhz with deep color pipe split no display 
the input to HW formula needs to take care the deep color.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:16:00 -04:00
Dmytro Laktyushkin
e51bf71e8c drm/amd/display: fix bw_calc for hdmi and 420 outputs 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:59 -04:00
Andrey Grodzovsky
cdc95cbb4c drm/amd/display: add preferred mode from Video Format Preference Data Block 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:55 -04:00
Eric Yang
1c3fb02d25 drm/amd/display: update clocks we report to PPlib 
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:51 -04:00
Dmytro Laktyushkin
cc408d726c drm/amd/display: mpc block redesign 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:49 -04:00
Leo (Sunpeng) Li
4fa086b9b6 drm/amd/display: Roll core_stream into dc_stream 
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:46 -04:00
Harry Wentland
e12cfcb1d4 drm/amd/display: Roll core_surface into dc_surface 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:35 -04:00
Charlene Liu
e63825be73 drm/amd/display: fix YCbCr420 deep color mode not supported 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:33 -04:00
Dmytro Laktyushkin
98e4a22f02 drm/amd/display: revert dcn10 soc defaults to 17 19 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:15:26 -04:00
Charlene Liu
2ebad8eb19 drm/amd/display: change non_dpm0 state's default SR latency 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:50 -04:00
Eric Yang
b884a2ec58 drm/amd/display: call pplib to update clocks 
Allow pplib to update fclk and dcfclk for different voltage levels.
PPlib's values for dispclk and phyclk is not correct, so we are not
getting it from them. fclk is currently not used correctly, although
does not effect the actual fclk we request.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:41 -04:00
Eric Yang
133e8e1b35 drm/amd/display: Change how we disable pipe split 
Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:40 -04:00
Eric Yang
966443b592 drm/amd/display: block modes that require read bw greater than 30% 
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:39 -04:00
Eric Yang
f42485bb6d drm/amd/display: move number of memory channel calc out of pplib call 
Move number of memory channel calculation out of dcn_bw_update_from_pplib

Fill in fabric_and_dram_bandwidth for single channel case.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:39 -04:00
Tony Cheng
d5d4e09f5d drm/amd/display: update DPM bounding box 
value based on STA  target aligned to FCLK for SS corners with 10% margin

also
- group all latency together
- group all voltage state related together

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:38 -04:00
Vitaly Prosyak
cdc5e04888 drm/amd/display: Fix for hdmi frame pack stereo 
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:28 -04:00
Dmytro Laktyushkin
cfe4645e17 drm/amd/display: fix dcn pipe reset sequence 
This change fixes dcn10 front end reset sequence. Previously we
would reset front end during flip which led to issues
in certain MPO and 4k/5k scenarios. We would also never properly
power gate our front end.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:22 -04:00
Dmytro Laktyushkin
afa80d64d2 drm/amd/display: fix bw_calc_auto translation error 
The compiler was warning about conditions that will never evaluate
to true. The problem was that the VBA translater didn't translate
the conditions correctly.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:12 -04:00
Dmytro Laktyushkin
5634fb6078 drm/amd/display: dcn bw_calc_auto update rev 247 to 250 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:11 -04:00
Dmytro Laktyushkin
139cb65c52 drm/amd/display: make variable latency into a regkey option 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:10 -04:00
Dmytro Laktyushkin
cb26f8925c drm/amd/display: use different sr latencies for dpm0 dcn bw calc 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:10 -04:00
Dmytro Laktyushkin
90f095c13e drm/amd/display: add pipe split disable regkey 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:07 -04:00
Vitaly Prosyak
7f5c22d165 drm/amd/display: RV stereo support 
HDMI frame pack and DP frame alternate in band

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:00 -04:00
Dmytro Laktyushkin
f0558542a7 drm/amd/display: redesign mpc 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:57 -04:00
Dmytro Laktyushkin
c9742685c2 drm/amd/display: add bw logging for dcn 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:56 -04:00
Harry Wentland
7fa4fcba7a drm/amd/display: Don't guard x86 in Makefile 
make-kpkg doesn't seem to like it

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:37 -04:00
Harry Wentland
bf2e2e2e0e drm/amd/display: Limit DCN to x86 arch 
DCN bw calcs currently rely on the following gcc options:
  -mhard-float -msse -mpreferred-stack-boundary=4

We probably shouldn't really try building this on architectures
other than x86.

CC: Alex Deucher <Alexander.Deucher@amd.com>
CC: Christian König <christian.koenig@amd.com>
CC: Michel Dänzer <michel.daenzer@amd.com>
CC: Tony Cheng <Tony.Cheng@amd.com>
CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:32 -04:00
Charlene Liu
ca3cba9c60 drm/amd/display: single channel bandwidth verses dual channel bandwidth 
DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth
for the rest of the DPM levels, single channel bandwidth = 1/2  dual channel bandwidth

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:04 -04:00
Yongqiang Sun
d4b4597384 drm/amd/display: Add 64KB_S_T and 64KB_D_T swizzle mode. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:03 -04:00
Dmytro Laktyushkin
9037d802a9 drm/amd/display: refactor bw related variable structure in val_ctx 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:01 -04:00
Dmytro Laktyushkin
64b44524d4 drm/amd/display: bw debug options now apply to dml as well 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:55 -04:00
Alex Deucher
ff5ef99248 drm/amdgpu/display: Enable DCN in DC 
Enable DCN in DC.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:51 -04:00
Harry Wentland
74c49c7ac1 drm/amdgpu/display: Add calcs code for DCN 
Bandwidth and scaling calculations for DCN.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:47 -04:00
Dmytro Laktyushkin
dff06ddd7f drm/amd/display: fix dce_calc surface pitch setting for non underlay pipes 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:22:03 -04:00
Harry Wentland
5e141de452 drm/amd/display: Rename bandwidth_calcs.h to dce_calcs.h 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:01 -04:00
Dmytro Laktyushkin
faddcb360c drm/amd/display: fix bw calc internal initialization error 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:19:57 -04:00
Logatharshan Thothiralingam
1de8c33bbd drm/amd/display: Fixed bandwidth calculation error when converting fractions 
[Problem]
VSR greyed out

[Root cause]
When converting fractions, we were using the integer function, which let to
a large display clock and the view was not supported

[Solution]
Change the integer to fraction functions

Signed-off-by: Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:19:49 -04:00
Alex Deucher
8fa9ca2ec6 drm/amd/display: Remove DCE12 guards 
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:19:36 -04:00
Alex Deucher
2c8ad2d5a2 drm/amd/display: Enable DCE12 support 
This wires DCE12 support into DC and enables it.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:19:23 -04:00
Dmytro Laktyushkin
4ef3a67b6a drm/amd/display: rename bandwidth_calcs.c to dce_calcs.c (v2) 
v2: agd: squash in the Makefile change as well.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Eagle Yeh <eagle.yeh@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:15:47 -04:00
Vitaly Prosyak
e266fdf694 drm/amd/display: Enable regamma 25 segments and use double buffer. 
Moved custom floating point calculation to the shared place
between dce's.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:14:18 -04:00
Vitaly Prosyak
ffbcd19a88 drm/amd/display: Adding 10 bpcc video P010 format 
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:13:40 -04:00
Tony Cheng
8693049a89 drm/amd/display: rename BGRA8888 to ABGR8888 
DC actually support ABGR8888 instead of BGRA8888 (R/B swap rather than endian swap) ,
rename to avoid confusion

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:11:00 -04:00
Amy Zhang
fcd2f4bf8b drm/amd/display: Output Transfer Function Regamma Refactor 
- Create translation function to translate logical format to hw format
- Refactor to use transfer function in dc instead of input gamma

Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:09:48 -04:00
Joshua Aberback
02dfc70737 drm/amd/display: Add Polaris12 to bw_calc 
Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:09:33 -04:00
Joshua Aberback
00c91d0d48 drm/amd/display: Support 64-bit Polaris11 5k VSR 
- pass full asic_id info into bw_calc_init instead of only version enum
- 64-bit Polaris11 needs an extra microsecond of dmif_urgent_latency
- add helper to convert from asic_id.family to bw_calc version enum

Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:09:20 -04:00
Harry Wentland
7a8b8b1403 drm/amd/display: Remove unused function in gamma_calcs 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:08:33 -04:00