Stephen Boyd
a8cd038cac
clk: mediatek: Export clk_ops structures to modules
...
modpost complains once these drivers become modules.
ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined!
Let's just export them.
Cc: Hanks Chen <hanks.chen@mediatek.com >
Cc: Wendell Lin <wendell.lin@mediatek.com >
Cc: Lee Jones <lee.jones@linaro.org >
Cc: Miles Chen <miles.chen@mediatek.com >
Fixes: 32b028fb1dhttps://lore.kernel.org/r/20210915015540.1732014-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 18:57:23 -07:00
Miles Chen
32b028fb1d
clk: mediatek: support COMMON_CLK_MEDIATEK module build
...
To support COMMON_CLK_MEDIATEK module build,
add MODULE_LICENSE and export necessary symbols.
Cc: Stephen Boyd <sboyd@kernel.org >
Cc: Hanks Chen <hanks.chen@mediatek.com >
Cc: Wendell Lin <wendell.lin@mediatek.com >
Cc: Lee Jones <lee.jones@linaro.org >
Signed-off-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210901222526.31065-3-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-09-14 18:20:20 -07:00
Chun-Jie Chen
710573dee3
clk: mediatek: Add MT8192 basic clocks support
...
Add MT8192 basic clock providers, include topckgen, apmixedsys,
infracfg and pericfg.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-10-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:07 -07:00
Chun-Jie Chen
197ee5436b
clk: mediatek: Get regmap without syscon compatible check
...
Not all clock providers need to be marked compatible with "syscon"
for system configuration usage, so use device_node_to_regmap() to
skip "syscon" check.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Link: https://lore.kernel.org/r/20210726105719.15793-6-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-07-27 10:53:06 -07:00
Laurent Pinchart
31a42c2f3b
clk: mediatek: mux: Update parent at enable time
...
The mux clocks don't always correctly take the new parent into account
when the parent is updated while the clock is disabled. Set the update
bit when enabling the clock to force an update of the mux.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Link: https://lore.kernel.org/r/20210125170819.26130-3-laurent.pinchart@ideasonboard.com
Reviewed-by: Weiyi Lu <weiyi.lu@mediatek.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-02-09 00:01:28 -08:00
Laurent Pinchart
6df3c6d9fd
clk: mediatek: mux: Drop unused clock ops
...
Three out of the four defined clock ops are unused. Drop them.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Link: https://lore.kernel.org/r/20210125170819.26130-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-02-09 00:01:28 -08:00
Weiyi Lu
2aeff9d8c8
clk: mediatek: Make mtk_clk_register_mux() a static function
...
mtk_clk_register_mux() should be a static function
Fixes: a3ae549917weiyi.lu@mediatek.com >
Link: https://lore.kernel.org/r/1605256192-31307-1-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-12-17 00:41:54 -08:00
Weiyi Lu
571cfadcc6
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
...
When some new clock supports are introduced, e.g. [1]
it might lead to an error although it should be NULL because
clk_init_data is on the stack and it might have random values
if using without initialization.
Add the missing initial value to clk_init_data.
[1] https://android-review.googlesource.com/c/kernel/common/+/1278046
Fixes: a3ae549917weiyi.lu@mediatek.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Cc: <stable@vger.kernel.org >
Link: https://lore.kernel.org/r/1590560749-29136-1-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-05-28 21:26:26 -07:00
Owen Chen
a3ae549917
clk: mediatek: Add new clkmux register API
...
On both MT8183 & MT6765, there add "set/clr" register for
each clkmux setting, and one update register to trigger value change.
It is designed to prevent read-modify-write racing issue.
The sw design need to add a new API to handle this hw change with
a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
Signed-off-by: Owen Chen <owen.chen@mediatek.com >
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com >
Reviewed-by: James Liao <jamesjj.liao@mediatek.com >
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org >
Tested-by: Nicolas Boichat <drinkcat@chromium.org >
[sboyd@kernel.org: Squash in flags=0 to silence warning]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 13:12:40 -07:00
