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786 Commits

Author SHA1 Message Date
Alan Liu
6880ed280e drm/amd/display: Add HDMI_ACP_SEND register 
Define HDMI_ACP_SEND register shift/mask.

Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-26 14:56:32 -04:00
Mohammad Zafar Ziya
0ae99221f3 drm/amdgpu/vcn: Add vcn ras poison consumption event handling 
Add vcn ras poison consumption event handling

V2: Removed default poison consumption handling function cb

Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-10 17:53:13 -04:00
Mohammad Zafar Ziya
7e0357fcf8 drm/amdgpu/jpeg: add jpeg ras poison consumption handling 
Add jpeg ras poison event callback and consumption handling

V2: Removed the default poison consumption cb handle

Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-10 17:53:13 -04:00
Likun Gao
1b49133042 drm/amdgpu: add lsdma block 
Add Light SDMA (LSDMA) block and related function. LSDMA
is a small instance of SDMA mainly for kernel driver use.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-10 17:53:11 -04:00
Hawking Zhang
81570d6dc2 drm/amdgpu: add lsdma v6_0_0 ip headers 
Add lsdma v6_0_0 register offset and shift masks
header files

v2: squash in updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-10 17:53:11 -04:00
Andrey Grodzovsky
bce04f216d drm/amd/psp: Add C2P registers to mp_13_0_2 header 
Add additional registers.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-06 16:58:10 -04:00
Huang Rui
c4d1c905ba drm/amdgpu: add hdp v5_2_1 ip headers 
Add hdp v5.2.1 offset and shift mask ip header files.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-06 10:36:13 -04:00
Huang Rui
4debe75395 drm/amdgpu: add nbio v7_7_0 ip headers 
Add nbio v7.7.0 offset and shift mask ip header files.

v2: squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-06 10:36:13 -04:00
Kenneth Feng
334682ae81 drm/amd/pm: enable workload type change on smu_v13_0_7 
enable workload type change on smu_v13_0_7

v2: squash in out of bounds fix (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-06 10:36:12 -04:00
Hawking Zhang
fd1e77d915 drm/amdgpu: add mmhub v3_0_2 ip headers 
Add mmhub v3_0_2 register offset and shift masks

v2: update to latest headers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:51:45 -04:00
Evan Quan
915b5ce774 drm/amdgpu: enable more GFX clockgating features for GC 11.0.0 
Support more GFX clockgating features(3D_CGCG, 3D_CGLS, MGCG,
FGCG and PERF_CLK).

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:50:58 -04:00
James Zhu
19dc81b401 drm/amdgpu: add irq sources for vcn v4_0 
Add the interrupt source packet definitions for VCN4.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:56 -04:00
Leo Liu
ed1db32e33 drm/amdgpu: add vcn 4_0_0 header files v7 
Add VCN 4.0.0 registers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:55 -04:00
Mukul Joshi
cc009e613d drm/amdkfd: Add KFD support for soc21 v3 
Add initial support for soc21 in KFD compute
driver (Mukul)
- Add new definition for soc21 device.
- Add new file for amdgpu-kfd interface for GFX11 family.
- Add new file for queue management, interrupt handling,
  mqd management for GFX11 family in KFD driver.
- Related changes/updates for soc21 device in
  KFD driver.
- Repurpose last 2 entries of SDMA MQD for driver use.

v2: Add an optional argument into update queue operation (Mukul)

v3: Switch to ip version check, replace kgd_dev with
    amdgpu_device (Hawking)

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:54 -04:00
Jack Xiao
028c3fb37e drm/amdgpu/mes11: initiate mes v11 support 
Initiate mes v11 code base from mes v10, rename function
and register names.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:54 -04:00
Jack Xiao
18ee4ce63e drm/amdgpu: add mes unmap legacy queue routine 
For mes kiq has been taken over by mes sched, drv can't directly
use mes kiq to unmap queues. drv has to use mes sched api to
unmap legacy queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:54 -04:00
Evan Quan
d6b9a91f5d drm/amdgpu: add FGCG support 
Add the CG flag for Fine Grained Clock Gating.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:56 -04:00
Wenhui Sheng
e6b5855555 drm/amdgpu: add irq src id for GFX11 
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:30 -04:00
Hawking Zhang
86a65c566e drm/amdgpu: add gfx11 mqd structures 
memory queue descriptors for gfx11.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:27 -04:00
Hawking Zhang
0eb1df055a drm/amdgpu: add soc21 chip enum header v8 
add soc21 enum definitions (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:18 -04:00
Hawking Zhang
21c8685b06 drm/amdgpu: add updated smu_info structures 
To match with smu v13_0_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:33 -04:00
Hawking Zhang
9f99d98305 drm/amdgpu: add mmhub v3_0_0 ip headers v6 
Add mmhub v3_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:16 -04:00
Hawking Zhang
f41c963972 drm/amdgpu: add athub v3_0_0 ip headers v6 
Add athub v3_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:06 -04:00
Hawking Zhang
55437d3bf4 drm/amdgpu: add smuio v13_0_6 ip headers v4 
Add smuio v13_0_6 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:54:35 -04:00
Hawking Zhang
11c4328a82 drm/amdgpu: add hdp v6_0_0 ip headers v4 
Add hdp v6_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:53:34 -04:00
Stanley.Yang
6e02c0ed4b drm/amdgpu: add ih v6_0 ip block v2 
This adds ih v6_0 ip block support.  IH is the
interrupt handler.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:53:12 -04:00
Stanley Yang
db56aebd81 drm/amdgpu: add soc21 ih clientid definition 
Define soc21 ih clientid

Signed-off-by: Stanley Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:52:59 -04:00
Hawking Zhang
d71093aa15 drm/amdgpu: add osssys v6_0_0 ip headers v4 
Add osssys v6_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:52:56 -04:00
Hawking Zhang
e19920c6a0 drm/amdgpu: add nbio v4_3_0 ip headers v6 
Add nbio v4_3_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:52:41 -04:00
Hawking Zhang
f33ac92f9c drm/amdgpu: add gc v11_0_0 ip headers v11 
Add gc v11_0_0 register offset and shift masks
header files (Hawking)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-28 17:48:28 -04:00
Hawking Zhang
85a41b429d drm/amdgpu: add mp v13_0_0 ip headers v7 
Add mp v13_0_0 register offset and shift masks
header files (Hawking)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-28 17:48:25 -04:00
Hawking Zhang
083e5ff641 drm/amdgpu: add atom_gfx_info_v3_0 structure 
atomfirmware table used for newer gfx IPs.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-28 17:48:13 -04:00
Hawking Zhang
1a4824488b drm/amdgpu: add vram_info v3_0 structure 
To support query vram_width, vram_type, vram_vendor
information

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-28 17:48:06 -04:00
Alex Deucher
005835233a drm/amdgpu: update latest IP discovery table structures 
Add new tables.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-28 17:46:31 -04:00
oushixiong
322687d596 drm/amd: Fix spelling typo in comment 
Signed-off-by: oushixiong <oushixiong@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-26 11:53:07 -04:00
Rongguang Wei
2530dc3cd3 drm/amdgpu: fix typo 
Fix spelling mistake:
	"differnt" -> "different"
	"commond"  -> "common"

Signed-off-by: Rongguang Wei <weirongguang@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-26 11:53:03 -04:00
David Zhang
5533347dbb drm/amd: add dc feature mask flags for PSR allow smu and multi-display optimizations 
[Why]
Allow for PSR SMU optimization and PSR multiple display optimization.

[How]
Add feature flags of PSR smu optimization and PSR multiple display
optimiztaion, and set them during init sequence. By default, flags
are disabled.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-26 11:51:36 -04:00
Lijo Lazar
73bce7a423 drm/amdgpu: Use flexible array member 
Use flexible array member in ip discovery struct as recommended[1].

[1] https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays

v2: squash in struct_size fixes

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-11 13:50:35 -04:00
Evan Quan
25faeddcf3 drm/amdgpu: expand cg_flags from u32 to u64 
With this, we can support more CG flags.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-08 17:24:24 -04:00
Mohammad Zafar Ziya
f0a339a8c0 drm/amdgpu/vcn: Add vcn and jpeg ver 2.6 ras register definition 
Adding vcn and jpeg ver 2.6 ras register definition

Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-03-28 12:54:39 -04:00
Xiaogang Chen
45f0ff404c drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK 
To fix applications running across multiple GPU config hang.

Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-24 17:24:43 -05:00
Qingqing Zhuo
5b723b1230 drm/amd/include: add DCN 3.1.5 registers 
Add DCN 3.1.5 and DPCS 4.2.2 register headers.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Change-Id: I5588a1c422ae384cc76aa42380545dfc1aad1948
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-18 14:07:00 -05:00
Yifan Zhang
62640f251f drm/amdgpu: add mp 13.0.5 header files 
This patch is to add mp 13.0.5 header files.

v2: update headers

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-18 14:07:00 -05:00
Leo Li
f3f6eff85f drm/amd/include: Add MP 13.0.8 register headers 
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-17 15:45:07 -05:00
Leo Li
64b14a184e drm/amd/include: Add register headers for DCN 3.1.6 
Add register headers for the following IPs:
- DCN 3.1.6
- DPCS 4.2.3

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-17 15:44:45 -05:00
Stanley.Yang
1ec1944eb5 drm/amdgpu: print more error info 
print more error info when deferred uncorrectable ras error

changed from V1:
    move Defferred error msg into query uncorrectable error
    count function.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-14 15:08:41 -05:00
Mukul Joshi
5bdd3eb253 drm/amdkfd: Remove unused old debugger implementation 
Cleanup the kfd code by removing the unused old debugger
implementation.
The address watch was only ever implemented in the upstream
driver for GFXv7 (Kaveri). The user mode tools runtime using
this API was never open-sourced. Work on the old debugger
prototype that used this API has been discontinued years ago.
Only a small piece of resetting wavefronts is kept and
is moved to kfd_device_queue_manager.c.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-09 16:57:51 -05:00
Alex Deucher
4a5dc6c73d drm/amdgpu: move dpcs_3_0_3 headers from dcn to dpcs 
To align with other headers.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-07 18:03:50 -05:00
Alex Deucher
68550cbc61 drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcs 
To align with other headers.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-07 18:03:50 -05:00
Alex Deucher
120cc6e67a drm/amdgpu: add missing license to dpcs_3_0_0 headers 
MIT.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-02-07 18:03:50 -05:00