leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,120,687 Commits 2 Branches 0 Tags
c235698355fa94df7073b51befda7d4be00a0e23
Commit Graph

15 Commits

Author SHA1 Message Date
Cai Huoqing
ee4abc4c5c clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource() 
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907085137.4407-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-01-05 16:43:41 -08:00
Dinh Nguyen
09540fa337 clk: socfpga: agilex: fix duplicate s2f_user0_clk 
Remove the duplicate s2f_user0_clk and the unused s2f_usr0_mux define.

Fixes: f817c132db ("clk: socfpga: agilex: fix up s2f_user0_clk representation")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210916225126.1427700-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-09-24 16:03:08 -07:00
Dinh Nguyen
d17929eb10 clk: socfpga: agilex: add the bypass register for s2f_usr0 clock 
Add the bypass register for the s2f_user0_clk.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-07-26 17:56:21 -07:00
Dinh Nguyen
f817c132db clk: socfpga: agilex: fix up s2f_user0_clk representation 
Correct the s2f_user0_mux clock representation.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-07-26 17:56:21 -07:00
Dinh Nguyen
9d563236cc clk: socfpga: agilex: fix the parents of the psi_ref_clk 
The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
not the C3.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-07-26 17:56:21 -07:00
Dinh Nguyen
c2c9c5661a clk: agilex/stratix10: add support for the 2nd bypass 
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that
was not being accounted for. The bypass selects between
emaca_clk/emacb_clk and boot_clk.

Because the bypass register offset is different between Stratix10 and
Agilex/N5X, it's best to create a new function to calculate the bypass.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-06-27 16:39:59 -07:00
Dinh Nguyen
6855ee8396 clk: agilex/stratix10: fix bypass representation 
Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp,
emac0/1/2) have a bypass setting that can use the boot_clk. The
previous representation was not correct.

Fix the representation.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-06-27 16:39:59 -07:00
Dinh Nguyen
efbe21df3e clk: agilex/stratix10: remove noc_clk 
Early documentation had a noc_clk, but in reality, it's just the
noc_free_clk. Remove the noc_clk clock and just use the noc_free_clk.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-06-27 16:39:59 -07:00
Stephen Boyd
abbe1eff90 clk: socfpga: Fix code formatting 
This function's parameters are oddly formatted. Looks like a newline was
missed or something. Fix it.

Cc: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210331023119.3294893-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-03-30 19:31:26 -07:00
Dinh Nguyen
ba7e258425 clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock
driver to use the clk_hw registration method.

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-03-30 19:26:26 -07:00
Dinh Nguyen
a0f9819cbe clk: socfpga: agilex: add clock driver for eASIC N5X platform 
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.

This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210212143059.478554-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2021-02-12 13:04:58 -08:00
YueHaibing
b10f224935 clk: socfpga: agilex: Remove unused variable 'cntr_mux' 
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=]
 static const struct clk_parent_data cntr_mux[] = {
                                     ^~~~~~~~

There is no caller in tree, so can remove it.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-09-22 12:46:12 -07:00
Dinh Nguyen
44a7f3e822 clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk 
Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-06-19 19:27:33 -07:00
Dinh Nguyen
6f3bcf56f8 clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk 
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-06-19 19:27:33 -07:00
Dinh Nguyen
80c6b7a089 clk: socfpga: agilex: add clock driver for the Agilex platform 
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-05-26 19:13:05 -07:00