Pull "SoCFPGA DTS updates for v4.15" from Dinh Nguyen:
- Stratix10 platform updates
- Fix up gic register entry
- Enable ethernet/SDMMC
- Update reset manager properties
* tag 'socfpga_dts_for_v4.15_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: add reset property for various peripherals
arm64: dts: stratix10: add the 'altr,modrst-off' property
arm64: dts: stratix10: include the reset manager bindings
arm64: dts: stratix10: add ethernet/sdmmc support to the S10 devkit
arm64: dts: stratix10: fix up the gic register for the Stratix10 platform
Pull "Renesas ARM Based SoC DT Updates for v4.15" from Simon Horman:
* r7s72100 (RZ/A1) Peach board
- Add pin groups for SCIF2 serial debug interface and Ethernet
This avoids relying on bootloader settings
- Support control of LED1 using gpio-leds
* r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
- Add MSIOF[012] support and define aliases for spi[0123]
* r8a7743 (RZ/G1M) SoC
- Add I2C and IIC core nodes
* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform
- Enable SDHI1 SD controller supporting high-speed and SDR50 transfers
- Add chosen node to allow correct selection of serial console
and the kernel command line
- Enable RTC support
- Enable USB2.0 host support
This includes enabling USB PHY and internal PCI
* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven and
r8a7745 (RZ/G1E) iW-RainboW-G22M-SM SoMs
- Enable Add SPI NOR support
This devices is used to boot up the system to the SoM DT
* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
- Enable SDHI0 SD controller supporting high-speed transfers
* r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
- Add pnctl support for scif4
This avoids reling on boot loader settings
- Add EtherAVB support
* r8a7745 (RZ/G1E) iW-RainboW-G22M-SM SoM
- Add basic SoM support
- Enable MMCIF eMMC support
- Enable RTC support
- Enable SDHI1 SD controller supporting high-speed transfers
* r8a779[0-4] R-Car Gen2 SoCs
- Add reset control properties
Geert Uytterhoeven says:
This patch series describes the reset topology on all R-Car Gen2 Socs,
like was done before for R-Car Gen3 and RZ/G1.
Resets usually match the corresponding module clocks. Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed upon request
from Laurent.
- Convert to new CPG/MSSR bindings
Geert Uytterhoven says:
Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2,
clk-mstp, and clk-div6 drivers, which depend on most clocks being
described in DT. Especially the module (MSTP) clocks are cumbersome
and error prone, due to 3 arrays (clocks, clock-indices, and
clock-output-names) to be kept in sync. In addition, the clk-mstp
driver cannot be extended easily to also support module resets, which
are provided by the same hardware module.
Hence when developing support for R-Car Gen3 SoCs, another approach
was chosen, which led to the CPG/MSSR driver core, and SoC-specific
subdrivers (initially for R-Car Gen3, but later also for RZ/G1).
This series converts the various R-Car Gen2 DTSes to migrate to the
new CPG/MSSR drivers that were added in v4.13-rc1.
* r8a779[0,1,3,4] R-Car Gen2 SoCs
- Stop grouping clocks under a "clocks" subnode
Geert Uytterhoeven says:
The current practice is to not group clocks under a "clocks" subnode,
but just put them together with the other on-SoC devices.
Hence this patch series implements this for the various R-Car Gen2
DTSes that still need this (r8a7792.dtsi is OK).
* r8a7794 (E2) Alt board
- Correct inverted sense of SD wip pins
* tag 'renesas-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (48 commits)
ARM: dts: r8a7743: Add MSIOF[012] support
ARM: dts: r8a7745: Add MSIOF[012] support
ARM: dts: iwg22d: Enable SDHI0 controller
ARM: dts: iwg22m: Add SPI NOR support
ARM: dts: r8a7745: Add QSPI support
ARM: dts: iwg20m: Add SPI NOR support
ARM: dts: r8a7743: Add QSPI support
ARM: dts: iwg22m: Enable SDHI1 controller
ARM: dts: r8a7745: Add SDHI controllers
ARM: dts: r8a7794: Add reset control properties
ARM: dts: r8a7793: Add reset control properties
ARM: dts: r8a7792: Add reset control properties
ARM: dts: r8a7791: Add reset control properties
ARM: dts: r8a7790: Add reset control properties
ARM: dts: r8a7743: Add IIC cores to dtsi
ARM: dts: alt: use correct logic for SD WP pins
ARM: dts: iwg20d-q7: Enable USB PHY
ARM: dts: iwg20d-q7: Enable internal PCI
ARM: dts: r8a7743: Link PCI USB devices to USB PHY
ARM: dts: r8a7743: Add USB PHY DT support
...
Pull "Renesas ARM Based SoC DT Bindings Updates for v4.15" from Simon Horman:
* Consistently do not use ';' in documentation of compat strings
for boards. A misture of using and not using a trailing ';' had
krept in over time with not using being dominant.
* Document bindings for
- Eagle board and r8a77970 (V3M) SoC bindings.
Eagle is a board for the V3M SoC
- Document Kingfisher board bindings.
Kingfisher is an extension board for the H3ULCB and M3ULCB boards.
* Add r8a77970 (V3M) SYSC power domain definitions
Add macros usable by the device tree sources to reference r8a77970 SYSC
power domains by index.
* Add Renesas SoC DT bindings doc to Renesas ARM section of MAINTAINERS file
* Drop bogus node name suffix from example of /renesas,dw-hdmi binding
* Document APMU and SMP enable method for r8a7745 (RZ/G1E) SoC
* tag 'renesas-dt-bindings-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: remove inconsistent ; from documentation
arm64: renesas: document Eagle board bindings
arm: shmobile: Document Kingfisher board DT bindings
dt-bindings: power: add R8A77970 SYSC power domain definitions
MAINTAINERS: Add Renesas SoC DT bindings doc to Renesas ARM sections
ARM: shmobile: Document R-Car V3M SoC DT bindings
dt-bindings: display: renesas: dw-hdmi: Drop bogus node name suffix
dt-bindings: apmu: Document r8a7745 support
Pull "Renesas ARM64 Based SoC DT Updates for v4.15" from Simon Horman:
* r8a7795 (H3)
- Use r8a7795-cpg-mssr and r8a7795-sysc bindings
Hardcoded indicies are replaced with symbols now that they are available
- Drop bogus HDMI node name suffixes
Laurent Pinchart says: Node names should not use numerical suffixes if
the nodes can be distinguished by unit-address
- Update PFC node name to pin-controller
Shimoda-san says the PFC node name is changed "from e6060000.pfc and
pfc@e6060000 to e6060000.pin-controller and pin-controller@e6060000
like other Renesas SoCs."
* r8a7795 (H3) ES1.0
- Drop extra zero from XHCI unit address
This corrects a typo were ee0400000 rather than ee040000 was used
as the unit address.
* r8a7796 (M3-W)
- Add FDP1 instance
Laurent Pinchart says: The r8a7796 has a single FDP1 instance.
* r8a7795 (H3) and r8a7796 (M3-W) SoCs
- Add USB3.0 peripheral device nodes
Shimoda-san says that this is not enabled on the Salvator-X/XS boards
for now as:
+ we need a special cable (USB type-A to A cross cable).
+ we can swap the role by renesas_usb3 driver even if we use a normal
cable and after usb3.0 host is running, but I think it's a special
use case.
* r8a7795 (H3) and r8a7796 (M3-W) ULCB boards
- Enable display output
Laurent Pinchart says: The DU is already wired up to the HDMI encoder,
all we need to do is enable it.
* r8a77995 (D3) Draak board
- Enable EthernetAVB and , USB2.0 Host and PHY
- Add serial console pins.
This is safe to do now that r8a77995 PFC driver support is present
* r8a77970 (V3M)
- Add basic support for SoC and EtherAVB, [H]SCIF and SYS-DMAC nodes
This is a step towards enabling EtherAVB and [H]SCIF with SYS-DMAC
in the Eagle board support for which is under review
* tag 'renesas-arm64-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
arm64: dts: renesas: r8a7796: add USB3.0 peripheral device node
arm64: dts: renesas: r8a7795: add USB3.0 peripheral device node
arm64: dts: renesas: r8a77995: draak: enable EthernetAVB
arm64: dts: renesas: r8a77995: draak: enable USB2.0 Host (EHCI/OHCI)
arm64: dts: renesas: r8a77995: draak: enable USB2.0 PHY
arm64: dts: renesas: r8a77995: add USB2.0 Host (EHCI/OHCI) device node
arm64: dts: renesas: r8a77995: Add USB2.0 PHY device node
arm64: dts: draak: Add serial console pins
arm64: dts: renesas: r8a77970: add EtherAVB support
arm64: dts: renesas: r8a77970: add [H]SCIF support
arm64: dts: renesas: r8a77970: add SYS-DMAC support
arm64: dts: renesas: initial R8A77970 SoC device tree
arm64: dts: renesas: r8a77995: Add EthernetAVB device node
arm64: dts: renesas: r8a77995: add GPIO device nodes
arm64: dts: renesas: r8a77995: Use r8a7795-cpg-mssr binding definitions
arm64: dts: renesas: r8a77995: Use r8a7795-sysc binding definitions
arm64: renesas: Add Renesas R8A77970 Kconfig support
arm64: dts: renesas: r8a7795: Drop bogus HDMI node names suffixes
arm64: dts: renesas: ulcb: Enable display output
arm64: dts: renesas: r8a77995: update PFC node name to pin-controller
...
Pull "DTS updates for the Integrator PCIv3 driver" from Linus Walleij:
These are the DTS file changes required to fix bugs and satisfy
requirements for the new PCIv3 driver in the PCI subsystem.
The binding changes have been merged to the PCI tree.
[arnd] Note: this is an incompatible DT binding change, so things
will break during bisection or when using an old dtb file.
Since integrator has no real users, we can make an exception
for that.
* tag 'integrator-pciv3-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Update Integrator/AP PCI v3 compatible
ARM: dts: integratorap: Fix PCI windows
ARM: dts: add the PCI clock to the device tree
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using
the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*'
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using
the following command:
perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*'
Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some
occurrences of uppercase hex.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
"interrupt-parent" property is declared in root node, so it is global
to all nodes. This property is re-declared in few sub-nodes. To avoid
duplication this property is removed from following sub-nodes:
pmu, amba@0, amba@0/ethernet.
Signed-off-by: Surender Polsani <surenderp@techveda.org>
Acked-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds interrupt-names property in audio node so that
binding can be agnostic of the IRQ order.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch adds board related config for MT2701 pwm backlight.
Signed-off-by: Weiqing Kong <weiqing.kong@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch adds the device node for MT2701 pwm backlight.
Signed-off-by: Weiqing Kong <weiqing.kong@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This adds the thermal sensor device provided by the BPMP, and the
relevant thermal sensors to the Tegra186 device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has three PCIe controllers, which can be operated
in 401, 211 or 111 lane combinations. Add DT support for
PCIe controllers.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a node for the Video Image Compositor on the Tegra186.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the node for Host1x on the Tegra186, without any subdevices
for now.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add #power-domain-cells for the BPMP node on Tegra186 so that the power
domain provider may be used.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
In Tegra186, the BPMP (Boot and Power Management Processor) implements
an interface that is used to read system temperatures, including CPU
cluster and GPU temperatures. This binding describes the thermal sensor
that is exposed by BPMP.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Try to add basic DT support for the Amlogic's Meson-AXG A113D SoC,
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Introduce new bindings for the Meson AXG SoC which now have
different memory layout.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the CEC controller on Jetson TK1 so that it can be used to
communicate with CEC devices via the HDMI connector.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add support for the Tegra CEC IP to the Tegra124 DTSI and link it to the
HDMI controller via phandle.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add node for xhci. Boards DT files will enable it if needed.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Various A10-based development boards have standard HDMI connectors
wired to the dedicated HDMI pins on the SoC.
Enable the display pipeline and HDMI output on boards I have or have
access to schematics:
- Cubieboard
- Olimex A10-OLinuXino-LIME
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All the A20 devices I own have standard HDMI connectors wired
to the dedicated HDMI pins on the SoC:
- Bananapi M1+
- Cubieboard 2
- Cubietruck
- Lamobo R1 (or Bananapi R1)
Development boards from Olimex also have standard HDMI connectors.
Schematics for them are publicly available. Enable HDMI on them as
well.
- Olimex A20-OLinuXino-LIME
- Olimex A20-OLinuXino-LIME2
- Olimex A20-OLinuXino-MICRO
Enable the display pipeline and HDMI output for them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Priit Laes <plaes@plaes.org> # Cubietruck, A20-OLinuXino-MICRO
Tested-by: Olliver Schinagl <oliver@schinagl.nl> # A20-OLinuXino-LIME2
Tested-by: Jonathan Liu <net147@gmail.com> # A20-OLinuXino-LIME
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 has two interconnected display pipelines, mirroring the A10.
Add all the device nodes for them, including the downstream HDMI
controller that we already support.
Signed-off-by: Jonathan Liu <net147@gmail.com>
[wens@csie.org: Squashed in HDMI and provided commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A10 has two interconnected display pipelines, much like the A31,
but without the DRCs between the backend and TCONs.
Add all the device nodes for them, including the downstream HDMI
controller that we already support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 SoC has a watchdog like the one on A20, in the timer memory zone
(which is also the same on A20).
Add the device tree node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Add usb otg support for rk3288-vyasa, board support usb1 otg
power through otg_vbus_drv and naming conversion followed
as per schematic.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add usb host support for rk3288-vyasa, board support hub power
through phy_pwr_en and usb2 host power through usb2_pwr_en and
naming conversion followed as per schematic.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the external clock-reference, enable the gmac node
and define the phy-related pin settings.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add supporting regulators for rk3288-vyasa board, dc12_vbat is
parent regulatorand followed regulators as are child regulators.
regulator naming conversion followed as per schematic for better
readability and easy for identification.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk808, SWITCH_REG1 has configured for sdmmc regulator as vcc_sd,
so use the same by renaming vcc33_sd to vcc_sd(as per schematic)
and drop explicit regulator definition from root.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
vdd_log, never used on DCDC_REG1 of rk808 from latest schematic so
remove the same and update the regulator-name as 'vdd_arm' to sync
with existing rk3288 board dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add thermal zone and dynamic CPU power coefficients for RV1108
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add tsadc needed main information for RV1108 SoC.
750000Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The sor1_src clock implemented on Tegra210 is modelled the wrong way
around, which causes some issues with HDMI and DP support. This clock
implementation is provided by BPMP on Tegra186, which models this in
a more correct way. Since this introduces incompatibilities between
the two SoC generations which we want to avoid, the Tegra210 will be
fixed in subsequent patches.
This change adds sor1_out as an alias for sor1_src.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds the USB pins and nodes for USB FS core on STM32F746 SoC.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch adds the USB pins and nodes for USB HS core on STM32F746 SoC.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Initially each pin was declared in "include/dt-bindings/stm32<SOC>-pinfunc.h"
and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).
Since this approach was approved, the number of supported MCU has
increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new
file in "include/dt-bindings" each time a new STM32 SOC arrives I propose
a new approach which consist to use a macro to define pin muxing in device
tree. All STM32 will use the common macro to define pinmux. Furthermore, it
will make STM32 maintenance and integration of new SOC easier .
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Reviewed-by: Vikas MANOCHA <vikas.manocha@st.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
