3 Commits

Author	SHA1	Message	Date
David Virag	e756e932a3	dt-bindings: clock: Add indices for Exynos7885 TREX clocks ... TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. Add indices for these clocks. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-3-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2022-06-20 13:57:20 +02:00
David Virag	cd268e309c	dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS ... CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, MMC_SDIO), and USB30DRD. Add clock indices and bindings documentation for CMU_FSYS domain. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2022-06-20 13:57:03 +02:00
David Virag	591020a516	dt-bindings: clock: Add bindings definitions for Exynos7885 CMU ... Just like on Exynos850, the clock controller driver is designed to have separate instances for each particular CMU, so clock IDs start from 1 for each CMU in this bindings header too. Signed-off-by: David Virag <virag.david003@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211206153124.427102-2-virag.david003@gmail.com	2021-12-19 23:37:54 +01:00