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5360 Commits

Author SHA1 Message Date
Eric Bernstein
b3a1cbc0c5 drm/amd/display: Expose is_rgb_cspace function in hw_sequencer 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:30 -05:00
Ken Chalmers
a6e59fa806 drm/amd/display: WBSCL filter init calculation fixes 
* Previous code did some calculations with a mix of normal integers and
  integers aligned as U2.24 fixed-point values.
* There were bugs in the conversion of the final result into the
  S4.19 values required for the registers.

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:29 -05:00
Eric Yang
f774b33982 drm/amd/display: remove unused function prototypes 
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:29 -05:00
Eric Yang
33fd17d912 drm/amd/display: fix cursor related Pstate hang 
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK

If graphics plane go from 1 pipe to hsplit, the cursor updates
after mpc programming and unlock. Which means there is a window
of time where cursor is enabled on the wrong pipe if it's on
the right side of the screen (i.e. case where cursor need to
move from pipe 0 to pipe 3 post split). This will cause pstate hang.

Solution is to program the cursor while still locked.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:28 -05:00
Yongqiang Sun
f9549850a4 drm/amd/display: Null check for gamma correction. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:27 -05:00
Yongqiang Sun
24a30505f3 drm/amd/display: Check hubp in pipe_ctx not in res_pool. 
When disable plane, check power gate flag in hubp with pipe_ctx,
not with res_pool.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:27 -05:00
Tony Cheng
c8ce5da527 drm/amd/display: dal 3.1.30 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:25 -05:00
John Barberiz
3e5df76ae5 drm/amd/display: Bypass gamma set if not standard type 
If non-standard gamma type detected set identity matrix flag
so that we can bypass the gamma mode.

Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:25 -05:00
Charlene Liu
69b9723a81 drm/amd/display: wait for T9 after backlight off mainlink blank. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:24 -05:00
Martin Tsai
ac916c914c drm/amd/display: Remove return when no EDID read. 
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:22 -05:00
Charlene Liu
c3b1c061f4 drm/amd/display: BL setting save/restore 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:22 -05:00
Arnd Bergmann
ac5d44fbf3 drm/amd/display: fix incompatible structure layouts 
Building the amd display driver with link-time optimizations revealed a bug
that caused dal_cmd_tbl_helper_dce80_get_table() and
dal_cmd_tbl_helper_dce110_get_table() get called with an incompatible
return type between the two callers in command_table_helper.c and
command_table_helper2.c:

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.h:31: error: type of 'dal_cmd_tbl_helper_dce80_get_table' does not match original declaration [-Werror=lto-type-mismatch]
 const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void);

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.c:351: note: 'dal_cmd_tbl_helper_dce80_get_table' was previously declared here
 const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void)

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.h:32: error: type of 'dal_cmd_tbl_helper_dce110_get_table' does not match original declaration [-Werror=lto-type-mismatch]
 const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void);

drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.c:361: note: 'dal_cmd_tbl_helper_dce110_get_table' was previously declared here
 const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void)

The two versions of the structure are obviously derived from the same
one, but have diverged over time, before they got added to the kernel.

This moves the structure to a new shared header file and uses the superset
of the members, to ensure the interfaces are all compatible.

Fixes: ae79c310b1 ("drm/amd/display: Add DCE12 bios parser support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:18 -05:00
Luis de Bethencourt
122fe39da4 drm: amd: Fix trailing semicolons 
The trailing semicolon is an empty statement that does no operation.
Removing the two instances of them since they don't do anything.

Signed-off-by: Luis de Bethencourt <luisbg@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:19:03 -05:00
Harry Wentland
f3b72c7b00 drm/amd/display: Fix warning about misaligned code 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:44 -05:00
John Barberiz
cf5620562f drm/amd/display: Add temporary delay on disconnect patch 
- Sequencing bug of not resetting delay on disconnect to default values

Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:44 -05:00
Mikita Lipski
6c1d03a4f2 drm/amd/display: Remove unnecessary register programming 
Remove aux engine register programming,when freeing the engine
as it was a temporary workaround.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:43 -05:00
John Barberiz
243c46c5ce drm/amd/display: Add temporary delay on disconnect patch 
Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:42 -05:00
Leo (Sunpeng) Li
9557080196 drm/amd/display: Fix unused variable compilation error 
Fix:

drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:
In function ‘dce110_blank_stream’:
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:1008:31:
error: unused variable ‘params’ [-Werror=unused-variable]
  struct encoder_unblank_param params = { { 0 } };

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:42 -05:00
Charlene Liu
41b497421a drm/amd/display: eDP sequence BL off first then DP blank. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:41 -05:00
Geling Li
cf5e4a67f4 drm/amd/display: Add debug flag for p010_mpo_support 
Signed-off-by: Geling Li <geling.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:41 -05:00
Krunoslav Kovac
a771c1f289 drm/amd/display: Force full update on pixel_format_change 
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:40 -05:00
Tony Cheng
352ab654ea drm/amd/display: dal 3.1.29 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:40 -05:00
Charlene Liu
7c357e61e2 drm/amd/display: dpms off mute az audio endpoint only. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:39 -05:00
Dmytro Laktyushkin
c7d76452d2 drm/amd/display: revert to hacking bounding box for pipe split 
Directly editing pipe config outside of formula is error prone
and results in higher clocks being used when splitting.
For this reason we reverted to using bounding box hacking
to split. Since sometimes this erroneusly results in higher dpm
being required we unhack the bounding box and recalculate to allow
dpm0 is possible.
Side effect is we will lose some stutter efficiency
in non dpm0 cases. This is not a big concern since increased stutter
efficiency saves an order of magnitude less power than lower dpm.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:38 -05:00
Charlene Liu
701ed303b2 drm/amd/display: disable az_clock_gating for endpoint register access only 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:38 -05:00
Arun Pandey
af1b00cdc6 drm/amd/display: Define dpp1_set_cursor_position in header 
Signed-off-by: Arun Pandey <Arun.Pandey@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:37 -05:00
Charlene Liu
cf1835f03f drm/amd/display: fix backlight not off at resume from S4 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:37 -05:00
Yongqiang Sun
3be1406a72 drm/amd/display: Add timing generator count to resource pool. 
Use tg count in resource pool for further reference.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:36 -05:00
SivapiriyanKumarasamy
05133ac856 drm/amd/display: Synchronize update plane addr for freesync 
Lock top_pipe when doing update plane addr for split pipe freesync case

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:36 -05:00
Harry Wentland
9182b4cb44 drm/amd/display: Call update_stream_signal directly from amdgpu_dm 
There's no good place in DC to cover all place where stream signal should
be updated. update_stream_signal depends on timing which comes from DM.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:35 -05:00
Yongqiang Sun
ff1374c94b drm/amd/display: Move output_tf to stream_state/update 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:34 -05:00
Ken Chalmers
b339743b89 drm/amd/display: Remove unused param in DML 
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:33 -05:00
Duke Du
3aa0caddf6 drm/amd/display: Update the register GRPH_SWAP_CNTL if surface pixel format changed. 
Signed-off-by: Duke Du <Duke.Du@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:33 -05:00
Harry Wentland
a27267e01f drm/amd/display: dc: Remove unused display_mode_vba.c 
We're currently not using this.

v2: More files and includes to remove.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:32 -05:00
Samuel Li
aa8e286a8a drm/amdgpu: rename amdgpu_get_crtc_scanoutpos 
Add display to the name for consistency.

Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:28 -05:00
Hawking Zhang
407e75170f drm/amd/dc: include new ip and ip_offset headers 
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:18:14 -05:00
Krunoslav Kovac
6d9ac917e6 drm/amd/display: [RS4][RV] SDR Brightness Boost 
We assume FP16 1.0 frame buffer value maps to 80 nits.
DC changes are to make this configurable.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:38 -05:00
Eric Bernstein
529c690ba8 drm/amd/display: Update dcn10_init_hw for FPGA 
Update dcn10_init_hw such that initialization of relevant
HW blocks for Maximus FPGA are also initialized (and not skipped).

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:37 -05:00
Leo (Sunpeng) Li
28dc87e41f drm/amd/display: Implement CRTC CRC for DCE110 
Implement the timing generator hooks for configure_crc and get_crc.
Also implement is_tg_enabled, as configure_crc uses it.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:37 -05:00
Leo (Sunpeng) Li
31aec354f9 drm/amd/display: Implement interface for CRC on CRTC 
Add interfaces in DC for per CRTC CRC configuration and fetching.
Also implement amdgpu_dm functions to hook onto DRM.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:36 -05:00
Eric Bernstein
8cb1545cad drm/amd/display: clean up DCHUBBUB register definition in hwseq 
Cleanup to remove unused register definition from hw sequencer
header file since implementation moved from hw sequencer to dchubub file.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:35 -05:00
Yongqiang Sun
365acbaf46 drm/amd/display: Refactor remove mpcc processing. 
No need to use loop find opp, use opp in stream_res.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:35 -05:00
Yongqiang Sun
be2f449a19 drm/amd/display: Move opp reg access from hwss to opp module. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:34 -05:00
Charlene Liu
c4bd27ac1a drm/amd/display: disablePSR in UpdatePlanes in PassiveLevel 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:34 -05:00
Roman Li
bc373a890f drm/amd/display: Fix null-derefs on non-dcn builds 
Fixing regression introduced by
'Use real BE and FE index to program regs.'

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:33 -05:00
Yongqiang Sun
f8e413bf3c drm/amd/display: Move dpp reg access from hwss to dpp module. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:33 -05:00
Yongqiang Sun
2e9d6a571c drm/amd/display: Check opplist in pipe ctx not in res pool. 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:32 -05:00
Andrew Jiang
405c50a07d drm/amd/display: Fix check for setting input TF 
We no longer change the plane state pointer for full updates, and as
such, we weren't setting the input transfer function and programming the
degamma registers when we are supposed to. Check for a full update, an
input TF change, or a gamma change in the update flags instead to correct
this.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:31 -05:00
Nikola Cornij
e56ae556e1 drm/amd/display: Define remove_stream_from_ctx resource func 
This will allow us to clean up resources on a stream as needed.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:30 -05:00
Harry Wentland
c7e74f4959 drm/amd/display: Log which clocks are unsupported 
It would be useful to know which clocks are unsupported when logging an
error message about unsupported clocks.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-02-19 14:17:29 -05:00