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Author SHA1 Message Date
Arnd Bergmann
888c173e31 Merge tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt 
STM32 DT for v5.20, round 1

Highlights:
----------

- MCU:
  -Fix whitespace coding style. No functional changes.

- MPU:
  - General:
    - Remove specific IPCC wakeup interrupt on STM32MP15.
    - Enable OPTEE firmware and scmi support (clock/reset) on
      STM32MP13. It allows to enable RCC clock driver.
    - Add new pins configurations groups.

  - DH boards:
    - Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN,
      uSD, USB, eMMC and SDIO wifi.
    - Add ST MIPID02 bindings to AV96 (not enabled by default)

  - OSD32:
    - Correct vcc-supply for eeprom.
    - fix missing internally connected voltage regulator (ldo3
      supplied by vdd_ddr).

* tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits)
  ARM: dts: stm32: Add ST MIPID02 bindings to AV96
  ARM: dts: stm32: Add alternate pinmux for RCC pin
  ARM: dts: stm32: Add alternate pinmux for DCMI pins
  ARM: dts: stm32: Add DHCOR based DRC Compact board
  ARM: dts: stm32: Add alternate pinmux for UART5 pins
  ARM: dts: stm32: Add alternate pinmux for UART4 pins
  ARM: dts: stm32: Add alternate pinmux for UART3 pins
  ARM: dts: stm32: Add alternate pinmux for SPI2 pins
  ARM: dts: stm32: Add alternate pinmux for CAN1 pins
  dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact
  ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15
  ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk
  ARM: dts: stm32: add RCC on STM32MP13x SoC family
  ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
  dt-bindings: rcc: stm32: select the "secure" path for stm32mp13
  ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32
  ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1
  ARM: dts: stm32: adjust whitespace around '=' on MCU boards
  ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
  ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151
  ...

Link: https://lore.kernel.org/r/a250f32b-f67c-2922-0748-e39dc791e95c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-06 13:46:26 +02:00
Arnd Bergmann
5b98b4021e Merge tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt 
AT91 DT for v5.20

It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
  controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
  with reality

* tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: lan966x: Add UDPHS support
  dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string
  ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.
  ARM: dts: lan966x: Add mcan1 node.
  ARM: dts: at91: sama7g5: add reset-controller node
  ARM: dts: at91: use generic name for reset controller
  ARM: dts: at91: sama5d2: fix compilation warning
  ARM: dts: at91: sama5d2: fix compilation warning

Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-06 13:42:46 +02:00
Arnd Bergmann
11303e4e4c Merge tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt 
Ux500 DTS updates for the v5.20 kernel:

- Fix orientation matrices on a few U8500 mobile phones.

- Drop unused i2c power supply handled by the power domain.

* tag 'ux500-dts-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
  ARM: dts: ux500: Drop unused i2c power domain supply
  ARM: dts: ux500: Fix Gavini accelerometer mounting matrix
  ARM: dts: ux500: Fix Codina accelerometer mounting matrix
  ARM: dts: ux500: Fix Janice accelerometer mounting matrix

Link: https://lore.kernel.org/r/CACRpkdY1MG=HG+tOCmD1_LEAStV1-ycCLkwShMRD4R=4jGDYHQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-06 13:41:57 +02:00
Arnd Bergmann
2630a9127c Merge tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt 
NFC flash node on rk3066a-mk808 and some dts styling fixes
(alignment and node names).

* tag 'v5.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: correct gpio-keys properties on rk3288-tinker
  ARM: dts: rockchip: align gpio-key node names with dtschema
  ARM: dts: rockchip: adjust whitespace around '='
  ARM: dts: rockchip: enable nfc node in rk3066a-mk808.dts

Link: https://lore.kernel.org/r/14795241.VsHLxoZxqI@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-06 13:40:11 +02:00
qianfan Zhao
7d655166db ARM: dts: sun8i-r40: Add thermal trip points/cooling maps 
For the trip points, I used values from the BSP code.

The critical trip point value is 30°C above the maximum recommended
ambient temperature (85°C) for the SoC from the datasheet, so there's
some headroom even at such a high ambient temperature.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220517013607.2252-4-qianfanguijin@163.com
 2022-07-05 21:40:18 +02:00
qianfan Zhao
14dbef6772 ARM: dts: sun8i-r40: add opp table for cpu 
OPP table value is get from allwinner lichee linux-3.10 kernel driver

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220517013607.2252-3-qianfanguijin@163.com
 2022-07-05 21:40:13 +02:00
qianfan Zhao
6d5f3f6758 ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based board 
The CPU of sun8i-r40 is powered by PMIC, let's add "cpu-supply" node.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220517013607.2252-2-qianfanguijin@163.com
 2022-07-05 21:35:57 +02:00
Krzysztof Kozlowski
3d34cae102 Merge branch 'for-v5.20/aspeed-dts-cleanup' into for-v5.20/dts-cleanup 2022-07-05 13:44:14 +02:00
Krzysztof Kozlowski
bafd5bb5ea ARM: dts: aspeed: correct gpio-keys properties 
gpio-keys children do not use unit addresses.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220616005333.18491-37-krzysztof.kozlowski@linaro.org
 2022-07-05 13:43:54 +02:00
Krzysztof Kozlowski
7bd809eee4 ARM: dts: aspeed: align gpio-key node names with dtschema 
The node names should be generic and DT schema expects certain pattern
(e.g. with key/button/switch).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220616005333.18491-36-krzysztof.kozlowski@linaro.org
 2022-07-05 13:43:37 +02:00
Marek Vasut
cc6280cf88 ARM: dts: stm32: Add ST MIPID02 bindings to AV96 
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT.
Both the ST MIPID02 and DCMI are disabled by default, as the
AV96 camera module is optional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
f95a5242c5 ARM: dts: stm32: Add alternate pinmux for RCC pin 
Add another mux option for RCC pin, this is used on AV96 board
for e.g. sensor clock supply.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
bcdf998ea3 ARM: dts: stm32: Add alternate pinmux for DCMI pins 
Add another mux option for DCMI pins, this is used on AV96 board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
49c66eb382 ARM: dts: stm32: Add DHCOR based DRC Compact board 
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
35b2cb537c ARM: dts: stm32: Add alternate pinmux for UART5 pins 
Add another mux option for UART5 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
ced0cb456b ARM: dts: stm32: Add alternate pinmux for UART4 pins 
Add another mux option for UART4 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
2ff9ec3a77 ARM: dts: stm32: Add alternate pinmux for UART3 pins 
Add another mux option for UART3 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
5eabbd30fe ARM: dts: stm32: Add alternate pinmux for SPI2 pins 
Add another mux option for SPI2 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
bdb1f18fa9 ARM: dts: stm32: Add alternate pinmux for CAN1 pins 
Add another mux option for CAN1 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Marek Vasut
fe7758e0e7 ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 11:42:11 +02:00
Herve Codina
4dd1a613e4 ARM: dts: lan966x: Add UDPHS support 
Add UDPHS (the USB High Speed Device Port controller) support.

The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS
IP. This IP is also the same as the one present in the SAMA5D3
SOC.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-4-herve.codina@bootlin.com
 2022-07-05 10:42:18 +03:00
Gabriel Fernandez
e007ec8422 ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk 
Add the static OP-TEE reserved memory regions.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Gabriel Fernandez
f95634becd ARM: dts: stm32: add RCC on STM32MP13x SoC family 
Enables Reset and Clocks Controller on STM32MP13

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Gabriel Fernandez
63058bfbda ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 
Enable optee and SCMI clocks support.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Leonard Göhrs
ef4ea690c5 ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32 
According to the OSD32MP1 Power System overview[1] the EEPROM is connected to
the VDD line and not to some single-purpose fixed regulator.
Set the EEPROM supply according to the diagram to eliminate this parent-less
regulator.

[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections

Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Leonard Göhrs
b2082d28d8 ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1 
According to the OSD32MP1 Power System overview[1] ldo3's input is always
internally connected to vdd_ddr.

[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections

Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Krzysztof Kozlowski
95a73a50da ARM: dts: stm32: adjust whitespace around '=' on MCU boards 
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Marek Vasut
1748c5c13e ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI 
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.

The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Fabien Dessenne
7d9802bb0e ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 
The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so
remove the unsupported "wakeup" one.
Note that the EXTI interrupt 61 has two roles : it is hierarchically linked
to the GIC IPCC "rx" interrupt, and it acts as a wakeup source.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-05 09:26:36 +02:00
Kavyasree Kotagiri
43a4ab4cf5 ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings. 
On pcb8291, Flexcom3 usart has only tx and rx pins.
Cleaningup usart3 pinctrl settings.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704135809.6952-1-kavyasree.kotagiri@microchip.com
 2022-07-05 10:25:57 +03:00
Kris Bahnsen
e95ea0f687 ARM: dts: imx6qdl-ts7970: Fix ngpio typo and count 
Device-tree incorrectly used "ngpio" which caused the driver to
fallback to 32 ngpios.

This platform has 62 GPIO registers.

Fixes: 9ff8e9fcce ("ARM: dts: TS-7970: add basic device tree")
Signed-off-by: Kris Bahnsen <kris@embeddedTS.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
 2022-07-05 09:06:47 +08:00
Sean Anderson
04069a86bf ARM: dts: layerscape: Add SFP node for TA 2.1 devices 
This adds an appropriate SFP node for Trust Architecture 2.1 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
 2022-07-05 09:04:14 +08:00
Linus Walleij
c6aaccf1c9 ARM: dts: ux500: Drop unused i2c power domain supply 
This regulator supply is replaced by the proper power
domain.

Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220701225339.814962-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-05 01:07:29 +02:00
Arnd Bergmann
9b47c57437 Merge tag 'omap-for-v5.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt 
Devicetree changes omaps for v5.20 merge window

Just one devicetree change to add EEPROM regulator for BeagleBone Black.

* tag 'omap-for-v5.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: am33xx: Map baseboard EEPROM on BeagleBone Black

Link: https://lore.kernel.org/r/pull-1656918942-515224@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-04 14:32:33 +02:00
Arnd Bergmann
c0d1a7bd65 Merge tag 'stm32-dt-for-v5.19-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/fixes 
STM32 DT fixes for v5.19, round 2

Highlights:
-----------

 -Fixes STM32MP15:
  - Add missing usbh clock and fix clk order for usbh to avoid PLL
    issue.
  - Fix SCMI version: use scmi regulator and update missing SCMI
    clocks to be able to correcly boot.

* tag 'stm32-dt-for-v5.19-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15
  ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI
  ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board
  ARM: dts: stm32: use the correct clock source for CEC on stm32mp151
  ARM: dts: stm32: fix pwr regulators references to use scmi

Link: https://lore.kernel.org/r/1259e082-a3a4-96a5-ec9c-05dbb893a746@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-04 14:29:19 +02:00
Fabrice Gasnier
1d0c1aadf1 ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be
initialized first, before enabling (gating) them. The reverse is also
required when going to suspend.
So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL
gets enabled 1st upon controller init. Upon suspend/resume, this also makes
the clock to be disabled/re-enabled in the correct order.
This fixes some IRQ storm conditions seen when going to low-power, due to
PHY PLL being disabled before all clocks are cleanly gated.

Fixes: 949a0c0dec ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c")
Fixes: db7be2cb87 ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-04 09:10:24 +02:00
Gabriel Fernandez
bf74181e75 ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI 
Delete the node fixed clock managed by secure world with SCMI.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-04 09:10:24 +02:00
Gabriel Fernandez
cfd7ea394c ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board 
LSE clock is provided by SCMI.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-04 09:10:24 +02:00
Gabriel Fernandez
78ece8cce1 ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 
The peripheral clock of CEC is not LSE but CEC.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-04 09:10:24 +02:00
Etienne Carriere
a34b42f869 ARM: dts: stm32: fix pwr regulators references to use scmi 
Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
regulators through SCMI service. This is needed since enabling secure
only access to RCC clock and reset controllers also enables secure
access only on PWR voltage regulators reg11, reg18 and usb33 hence
these must also be accessed through SCMI Voltage Domain protocol.
This change applies on commit [2] that already corrects issues from
commit [1].

Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
 2022-07-04 09:10:24 +02:00
Kavyasree Kotagiri
3e6fd02fce ARM: dts: lan966x: Add mcan1 node. 
Add the mcan1 node. By default, keep it disabled.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220627110552.26315-1-kavyasree.kotagiri@microchip.com
 2022-07-04 09:40:15 +03:00
Claudiu Beznea
d657ab8447 ARM: dts: at91: sama7g5: add reset-controller node 
Add reset controller node.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220610092414.1816571-10-claudiu.beznea@microchip.com
 2022-07-04 08:34:03 +03:00
Claudiu Beznea
979813d2ab ARM: dts: at91: use generic name for reset controller 
Use generic name for reset controller of AT91 devices to comply with
DT specifications.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
 2022-07-04 08:34:03 +03:00
Claudiu Beznea
b66724d23d ARM: dts: at91: sama5d2: fix compilation warning 
Fix the following compilation warning:
arch/arm/boot/dts/sama5d2.dtsi:371.29-382.6: Warning
(avoid_unnecessary_addr_size): /ahb/apb/ethernet@f8008000:
unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
also defined at arch/arm/boot/dts/at91-sama5d2_icp.dts:353.8-363.3

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220615080633.1881196-2-claudiu.beznea@microchip.com
 2022-07-04 08:34:03 +03:00
Claudiu Beznea
005627ea13 ARM: dts: at91: sama5d2: fix compilation warning 
Fix the following compilation warning:
Warning (simple_bus_reg): /ahb/apb/resistive-touch: missing or empty reg/ranges property

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220615080633.1881196-1-claudiu.beznea@microchip.com
 2022-07-04 08:34:03 +03:00
Bhupesh Sharma
2477d81901 ARM: dts: qcom: Fix sdhci node names - use 'mmc@' 
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Extracted from combined arm64 patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
 2022-07-02 22:20:56 -05:00
Arnd Bergmann
d5444cc4cb Merge tag 'amlogic-arm-dt-for-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/dt 
Amlogic ARM DT changes for v5.20:
- adjust whitespace around '=' in ARM meson DT

* tag 'amlogic-arm-dt-for-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  ARM: dts: meson: adjust whitespace around '='

Link: https://lore.kernel.org/r/51034acd-13db-5c25-7b9f-ff87537406bd@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-01 16:15:24 +02:00
Arnd Bergmann
7ccd1f6dce Merge tag 'dt-cleanup-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt 
Cleanup of ARM DTS for v5.20

Series of cleanups for ARM DTS:
1. White-spaces, gpio-key subnode names, USB DWC3/EHCI node names,
2. Add board-level compatibles to Aspeed evaluation boards.

* tag 'dt-cleanup-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: stih407-family: Harmonize DWC USB3 DT nodes name
  ARM: dts: lpc18xx: Harmonize EHCI/OHCI DT nodes name
  ARM: dts: ast2600-evb-a1: fix board compatible
  ARM: dts: ast2600-evb: fix board compatible
  ARM: dts: ast2500-evb: fix board compatible
  ARM: dts: animeo: correct gpio-keys properties
  ARM: dts: animeo: align gpio-key node names with dtschema
  ARM: dts: sd: adjust whitespace around '='
  ARM: dts: sti: adjust whitespace around '='
  ARM: dts: ste: adjust whitespace around '='
  ARM: dts: nuvoton: adjust whitespace around '='
  ARM: dts: lpc: adjust whitespace around '='
  ARM: dts: ecx: adjust whitespace around '='
  ARM: dts: alpine: adjust whitespace around '='
  ARM: dts: spear: adjust whitespace around '='
  ARM: dts: axm: adjust whitespace around '='
  ARM: dts: at91: adjust whitespace around '='
  ARM: dts: aspeed: adjust whitespace around '='
  ARM: dts: pxa: adjust whitespace around '='

Link: https://lore.kernel.org/r/20220627082842.50508-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-01 16:14:17 +02:00
Arnd Bergmann
3966af4055 Merge tag 'socfpga_dts_updates_for_v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt 
SoCFPGA dts updates for v5.20
- Clean up the Mercury++ AA1 dts
- Add support the Google Chameleon v3 board
- Add defined GIC interrupt type for Agilex ECC
- Fix coding style around Stratix10 QSPI dts entry
- Add support for Stratix10 SW Virtual platform
- Move clocks entry out of the Stratix10 soc node

* tag 'socfpga_dts_updates_for_v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
  arm64: dts: Add support for Stratix 10 Software Virtual Platform
  dt-bindings: altera: document Stratix 10 SWVP compatibles
  arm64: dts: altera: adjust whitespace around '='
  arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
  dt-bindings: altera: Add Chameleon v3 board
  ARM: dts: socfpga: Add Google Chameleon v3 devicetree
  ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
  ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
  ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi

Link: https://lore.kernel.org/r/20220626004437.1224820-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-01 16:11:59 +02:00
Arnd Bergmann
4505bb959a Merge tag 'renesas-arm-dt-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt 
Renesas ARM DT updates for v5.20

  - ADC and SPI support for the RZ/G2UL Soc and the RZ/G2UL SMARC EVK
    development board,
  - Ethernet support for the RZ/V2M SoC and the RZV2MEVK2 development
    board,
  - Thermal, IOMMU, Universal Flash Storage, octal Cortex-A55, and full
    serial support for the R-Car S4-8 SoC on the Spider development
    board,
  - RTC support for the RZN1D-DB board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
  ARM: dts: rza2mevb: Fix LED node names
  arm64: dts: renesas: Fix thermal-sensors on single-zone sensors
  arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector
  arm64: dts: renesas: r8a779f0: Add SCIF nodes
  arm64: dts: renesas: r8a779f0: Add HSCIF nodes
  arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3
  arm64: dts: renesas: Add missing space after remote-endpoint
  arm64: dts: renesas: rzg2ul-smarc-som: Enable ADC on SMARC platform
  arm64: dts: renesas: rzg2ul-smarc: Enable RSPI1 on carrier board
  arm64: dts: renesas: r8a779f0: Add CPU core clocks
  arm64: dts: renesas: r8a779f0: Add CPUIdle support
  arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
  arm64: dts: renesas: r8a779f0: Add L3 cache controller
  arm64: dts: renesas: r8a779a0: Add CPU0 core clock
  arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
  ARM: dts: r9a06g032-rzn1d400-db: Enable rtc0
  arm64: dts: renesas: rzg2l-smarc: Use proper bool operator
  arm64: dts: renesas: r8a779f0: Add UFS node
  arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodes
  arm64: dts: renesas: r8a779f0: Add IPMMU nodes
  ...

Link: https://lore.kernel.org/r/cover.1656069634.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-01 16:03:01 +02:00