Paul M Stillwell Jr
3ba3faeb62
i40e/i40evf: Big endian fixes for handling HMC
...
Fix HMC handling for big endian architectures.
Change-ID: Id8c46fc341815d47bfe0af8b819f0ab9a1e9e515
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com >
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com >
2014-06-26 04:44:57 -07:00
Jesse Brandeburg
b831607d34
i40evf: Fix the headers and update copyright year.
...
Adding the appropriate GNU General Public License header and
update copyright year to 2014.
Change-ID: I769dd2d37d70350afd0c8727ae2859c0fd340361
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com >
Signed-off-by: Catherine Sullivan <catherine.sullivan@intel.com >
Tested-by: Sibai Li <sibai.li@intel.com >
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com >
2014-05-21 01:54:43 -07:00
Jesse Brandeburg
0b3aec852b
i40e/i40evf: unhide and enable to one prefena field
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The PREFENA field in the receive host memory cache (RX-HMC)
must be visible in order to be set to 1 at driver init for
best performance.
Change-ID: I16b0bcd84cf56f4b6c938201ff5e954bee5a1992
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com >
Acked-by: Shannon Nelson <shannon.nelson@intel.com >
Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com >
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com >
2014-04-21 20:35:42 -07:00
Greg Rose
90327e7dff
i40evf: A0 silicon specific
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A0 stepping silicon specific code
Signed-off-by: Greg Rose <gregory.v.rose@intel.com >
Tested-by: Sibai Li <sibai.li@intel.com >
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com >
2013-12-31 16:39:42 -08:00
Greg Rose
d358aa9a7a
i40evf: init code and hardware support
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This patch implements the hardware specific init and management.
Signed-off-by: Mitch Williams <mitch.a.williams@intel.com >
Signed-off-by: Greg Rose <gregory.v.rose@intel.com >
Tested-by: Sibai Li <sibai.li@intel.com >
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com >
2013-12-31 16:18:25 -08:00
