Sonny Jiang
0b37f47494
drm/amdgpu: Enable VCN DPG for GC11_0_1
...
Enable VCN DPG on GC11_0_1
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com >
Reviewed-by: James Zhu <James.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-09-30 11:20:43 -04:00
Candice Li
34dfca8908
drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0
...
Enable full reset for RAS supported configuration on gc v11_0_0.
v2: simplify the code.
Signed-off-by: Candice Li <candice.li@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-09-13 12:56:16 -04:00
Jane Jian
c322b422ab
drm/amdgpu/vcn: Disable CG/PG for SRIOV
...
For sriov, CG and MG are controlled from hypervisor side,
no need to manage them again in ip init
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Jane Jian <Jane.Jian@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-09-01 15:12:00 -04:00
Yifan Zha
8284182592
drm/admgpu: Skip CG/PG on SOC21 under SRIOV VF
...
[Why]
There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF.
For multi VF, VF should not enable any CG/PG features.
For one VF, PF will program CG/PG related registers.
[How]
Do not set any cg/pg flag bit at early init under sriov.
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-09-01 15:11:54 -04:00
Yifan Zha
bbb860d46f
drm/amdgpu: Use RLCG to program GRBM_GFX_CNTL during full access time
...
[Why]
KIQ register init requires GRBM_GFX_CNTL to select KIQ.
[How]
As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it.
Use RLCG indirect accessing register method to select grbm instead of mmio directly access.
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-09-01 15:11:50 -04:00
Sonny Jiang
0f05a2e528
drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCN
...
This enable VCN PG, CG, DPG and JPEG PG, CG
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com >
Reviewed-by: Leo Liu <leo.liu@amd.com >
Reviewed-by: John Clements <john.clements@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-29 17:59:30 -04:00
Hawking Zhang
6b46251c50
drm/amdgpu: initialize common sw config for v11_0_3
...
init cp/pg_flags and extenal_rev_id
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Frank Min <Frank.Min@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-29 17:59:30 -04:00
Likun Gao
7201023910
drm/amdgpu: add MGCG perfmon setting for gfx11
...
Enable GFX11 MGCG perfmon setting.
V2: set rlc to saft mode before setting.
Signed-off-by: Likun Gao <Likun.Gao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-25 13:35:18 -04:00
Tim Huang
9407feacd2
drm/amdgpu: enable NBIO IP v7.7.0 Clock Gating
...
Enable AMD_CG_SUPPORT_BIF_MGCG and AMD_CG_SUPPORT_BIF_LS support.
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-22 16:47:28 -04:00
Tim Huang
fa0bbd3be9
drm/amdgpu: enable IH Clock Gating for OSS IP v6.0.1
...
Enable AMD_CG_SUPPORT_IH_CG support.
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-16 18:06:54 -04:00
Tim Huang
8e78c7c4fe
drm/amdgpu: enable ATHUB IP v3.0.1 Clock Gating
...
Enable AMD_CG_SUPPORT_ATHUB_MGCG and AMD_CG_SUPPORT_ATHUB_LS support.
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-16 18:06:18 -04:00
Tim Huang
7e4a77de08
drm/amdgpu: enable HDP IP v5.2.1 Clock Gating
...
Enable AMD_CG_SUPPORT_HDP_MGCG and AMD_CG_SUPPORT_HDP_LS support.
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-16 18:06:11 -04:00
Tim Huang
adcd15dc47
drm/amdgpu: enable MMHUB IP v3.0.1 Clock Gating
...
Enable AMD_CG_SUPPORT_MC_MGCG and AMD_CG_SUPPORT_MC_LS support.
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-16 18:06:06 -04:00
Kenneth Feng
b4ddb27d1d
drm/amd/amdgpu: add ih cg and hdp sd on smu_v13_0_7
...
add ih cg and hdp sd on smu_v13_0_7
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-16 18:03:10 -04:00
Evan Quan
1b586595df
drm/amdgpu: disable 3DCGCG/CGLS temporarily due to stability issue
...
Some stability issues were reported with these features.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-16 18:02:42 -04:00
Tim Huang
dc0a096bcc
drm/amdgpu: add GFX Power Gating support for GC IP v11.0.1
...
Add AMD_PG_SUPPORT_GFX_PG support.
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-10 15:41:23 -04:00
Tim Huang
8df436d5cc
drm/amdgpu: add GFX Clock Gating support for GC IP v11.0.1
...
Add below GFX Clock Gating supports:
1. GFX Coarse Grain Clock Gating(CGCG)
2. GFX Coarse grain light sleep/deep sleep(CGLS)
3. GFX Medium Grain Clock Gating(MGCG)
4. GFX Fine Grain Clock Gating(FGCG)
5. Repeater Fine Grain Clock Gating
6. Perfmon Clock Gating
Signed-off-by: Tim Huang <tim.huang@amd.com >
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-08-10 15:10:19 -04:00
Sonny Jiang
47231d5e39
drm/amdgpu: enable VCN cg and JPEG cg/pg
...
Not enable VCN pg because encode issue
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com >
Reviewed-by: James Zhu <James.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-28 16:28:54 -04:00
Sonny Jiang
1c0a903648
drm/amdgpu: vcn_4_0_2 video codec query
...
Enable support for vcn_4_0_2 video codec
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com >
Reviewed-by: James Zhu <James.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-28 16:28:54 -04:00
Kenneth Feng
a53bc32182
drm/amd/pm: enable mode1 reset for smu_v13_0_7
...
enable mode1 reset for smu_v13_0_7 since it's missing.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com >
Reviewed-by: Yang Wang <kevinyang.wang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Likun Gao
c0ff84cb58
drm/amdgpu: enable soft reset for gfx 11
...
Enable soft reset for gfx 11.
V2: enable both gfx v11.0.0 and gfx v11.0.2.
Signed-off-by: Likun Gao <Likun.Gao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-13 11:25:16 -04:00
Evan Quan
62f8f5c3bf
drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0
...
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-06-08 11:43:00 -04:00
Alex Deucher
ea64228d26
drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
...
Set the default reset method to mode2 for SMU IP v13.0.4
Acked-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Tim Huang <Tim.Huang@amd.com >
Signed-off-by: Tim Huang <tim.huang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-06-06 14:43:47 -04:00
Kenneth Feng
49401d3a5c
drm/amd/amdgpu: align the cg and pg settings
...
align the cg and pg settings between gc_v11_0 and gc_v11_2
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-06-03 16:43:38 -04:00
Evan Quan
caa5eadc14
drm/amdgpu: suppress some compile warnings
...
Suppress two compile warnings about "no previous prototype".
Reported-by: kernel test robot <lkp@intel.com >
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-26 14:56:33 -04:00
Likun Gao
362c3c7014
drm/amdgpu: support memory power gating for lsdma 6.0.2
...
Support memory power gating control for lsdma 6.0.2.
Signed-off-by: Likun Gao <Likun.Gao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-10 17:53:12 -04:00
Likun Gao
41967850e4
drm/amdgpu: support memory power gating for lsdma
...
Support memory power gating control for LSDMA.
Signed-off-by: Likun Gao <Likun.Gao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-10 17:53:12 -04:00
Alex Deucher
bf1781e17f
drm/amdgpu: simplify nv and soc21 read_register functions
...
Check of the base offset for the IP exists rather than
explicitly checking for how many instances of a particular
IP there are. This is what soc15.c already does. Expand
this to nv.c and soc21.c.
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-06 16:56:57 -04:00
Huang Rui
11417a927b
drm/amdgpu: add soc21 common ip block support for GC 11.0.1
...
Add common soc21 ip block support for GC 11.0.1.
Signed-off-by: Huang Rui <ray.huang@amd.com >
Reviewed-by: Aaron Liu <aaron.liu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-06 10:36:14 -04:00
Xiaojian Du
bafd6cbe4a
drm/amdgpu: add pcie port function helpers for SOC21
...
These helpers will be used on NBIO v7.7.0.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-06 10:36:13 -04:00
Xiaojian Du
06aeb75332
drm/amdgpu: handle asics with 1 SDMA instance
...
This patch will handle asics with 1 SDMA instance.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com >
Reviewed-by: Huang Rui <ray.huang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-06 10:36:13 -04:00
Kenneth Feng
27e3911c40
drm/amd/soc21: enable mmhub and athub power gating
...
add the pg_flag for athub and mmhub pg.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com >
Reviewed-by: Jack Gui <Jack.Gui@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:53:44 -04:00
Likun Gao
9503a944e7
drm/amdgpu: enable cgcg and cgls for GC 11_0_2
...
Enable GFX CGCG and CGLS for GFX v11_0_2.
Signed-off-by: Likun Gao <Likun.Gao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:53:00 -04:00
James Zhu
ec9db74e1a
drm/amdgpu/vcn: enable VCN DPG mode for VCN4_0_4
...
Enable VCN DPG mode for VCN4_0_4.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:52:21 -04:00
James Zhu
143a34a0ac
drm/amdgpu/vcn: enable VCN PG for VCN4_0_4
...
Enable VCN PG for VCN4_0_4.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:52:18 -04:00
James Zhu
7ece9314a4
drm/amdgpu/vcn: enable VCN CG for VCN4_0_4
...
Enable VCN CG for VCN4_0_4.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:52:16 -04:00
James Zhu
ebac66a328
drm/amdgpu/jpeg: enable JPEG PG for VCN4_0_4
...
Enable JPEG PG for VCN4_0_4.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:52:14 -04:00
James Zhu
71dae22143
drm/amdgpu/jpeg: enable JPEG CG for VCN4_0_4
...
Enable JPEG CG for VCN4_0_4.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:52:12 -04:00
Flora Cui
92fd215314
drm/amdgpu: add soc21 support for GC 11.0.2
...
Add initial soc21 support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Flora Cui <flora.cui@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:51:24 -04:00
Evan Quan
d386f64588
drm/amdgpu: enable clock gating for HDP 6.0
...
Enable HDP 6.0 clock gating.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:51:21 -04:00
Evan Quan
2013906955
drm/amdgpu: enable clock gating for IH 6.0
...
Enable IH 6.0 clock gating.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:51:17 -04:00
Evan Quan
7ccf6eb003
drm/amdgpu: enable MGCG and LS for MMHUB 3.0
...
Enable MMHUB 3.0 MGCG and LS features.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:51:14 -04:00
Evan Quan
c649ed054a
drm/amdgpu: enable MGCG and LS for ATHUB 3.0
...
Enable ATHUB 3.0 MGCG and LS features.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:51:11 -04:00
Evan Quan
915b5ce774
drm/amdgpu: enable more GFX clockgating features for GC 11.0.0
...
Support more GFX clockgating features(3D_CGCG, 3D_CGLS, MGCG,
FGCG and PERF_CLK).
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Likun Gao <Likun.Gao@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-05 16:50:58 -04:00
James Zhu
9ac0edaa0f
drm/amdgpu: add vcn_4_0_0 video codec query
...
Add vcn_4_0_0 video codec query.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Leo Liu <leo.liu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:56 -04:00
James Zhu
04270390fe
drm/amdgpu/vcn: enable vcn4 dpg mode
...
Enable vcn4 dpg mode.
Signed-off-by: James Zhu <James.Zhu@amd.com >
Reviewed-by: Leo Liu <leo.liu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:56 -04:00
James Zhu
7c507d35a5
drm/amdgpu/jpeg: enable JPEG PG and CG for VCN4_0_0
...
Enable JPEG PG and CG for VCN4_0_0.
Reviewed-by: Leo Liu <leo.liu@amd.com >
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: James Zhu <James.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:56 -04:00
Leo Liu
8b719b968f
drm/amdgpu: enable VCN4 PG and CG for VCN4_0_0
...
Most of the tiles can be power/clock gated.
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Leo Liu <leo.liu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:56 -04:00
Evan Quan
b21348a28b
drm/amdgpu: enable fgcg for soc21
...
Enable Fine Grained Clock Gating on soc21 asics.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:54 -04:00
Evan Quan
390db4b84a
drm/amdgpu: enable GFX CGCG/CGLS for GC11.0.0
...
Enable GFX CGCG (coarse grained clockgating) and
CGLS (coarse grained light sleep) for GC11.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Likun Gao <Likun.Gao@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:54 -04:00