Commit Graph

4 Commits

Author SHA1 Message Date
Mikko Rapeli
adb8a5a5eb uapi drm/armada_drm.h: use __u32 and __u64 instead of uint32_t and uint64_t
These are defined in linux/types.h or drm/drm.h. Fixes
user space compilation errors like:

drm/armada_drm.h:26:2: error: unknown type name ‘uint32_t’
  uint32_t handle;
  ^~~~~~~~

Signed-off-by: Mikko Rapeli <mikko.rapeli@iki.fi>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Gabriel Laskar <gabriel@lse.epita.fr>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20170806164428.2273-33-mikko.rapeli@iki.fi
2017-08-07 17:01:15 +02:00
Emil Velikov
1224649a9c drm/armada: add extern C guard for the UAPI header
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2016-05-13 13:57:02 +01:00
Gabriel Laskar
6a14d01b91 drm: include drm.h in armada_drm.h
Signed-off-by: Gabriel Laskar <gabriel@lse.epita.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
CC: Emil Velikov <emil.l.velikov@gmail.com>
CC: Mikko Rapeli <mikko.rapeli@iki.fi>
2015-12-10 12:33:23 +01:00
Russell King
96f60e37dc DRM: Armada: Add Armada DRM driver
This patch adds support for the pair of LCD controllers on the Marvell
Armada 510 SoCs.  This driver supports:
- multiple contiguous scanout buffers for video and graphics
- shm backed cacheable buffer objects for X pixmaps for Vivante GPU
  acceleration
- dual lcd0 and lcd1 crt operation
- video overlay on each LCD crt via DRM planes
- page flipping of the main scanout buffers
- DRM prime for buffer export/import

This driver is trivial to extend to other Armada SoCs.

Included in this commit is the core driver with no output support; output
support is platform and encoder driver dependent.

Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-10-12 10:13:40 +01:00