UFS proprietary features (including features introduced later) in MediaTek
UFS platforms have complicated combinations among different platforms.
To ease code readability and maintenance, decouple all proprietary features
from platform bindings. Each feature would be enabled only if specific
property string is defined in device tree node.
Link: https://lore.kernel.org/r/20201029115750.24391-4-stanley.chu@mediatek.com
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Some MediaTek UFS platforms support high-performance mode that inline
encryption engine can be boosted while UFS is not clock-gated.
The high-performance mode will be enabled if all below conditions are
well-declaired in device tree,
- Proper platform-specific compatible string which enables the host
capability "UFS_MTK_CAP_BOOST_CRYPT_ENGINE".
- "dvfsrc-vcore" node is available in this platform.
- Required minimum vcore voltage for high-performance mode.
- Clock mux and clock parents of inline encryption engine for both
"low-power mode" and "high-performance mode".
Link: https://lore.kernel.org/r/20200914050052.3974-2-stanley.chu@mediatek.com
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Add inline encryption support to ufs-mediatek.
The standards-compliant parts, such as querying the crypto capabilities and
enabling crypto for individual UFS requests, are already handled by
ufshcd-crypto.c, which itself is wired into the blk-crypto framework.
However MediaTek UFS host requires a vendor-specific hce_enable operation
to allow crypto-related registers being accessed normally in kernel. After
this step, MediaTek UFS host can work as standard-compliant host for
inline-encryption related functions.
Link: https://lore.kernel.org/r/20200712003226.7593-1-stanley.chu@mediatek.com
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
MediaTek UFS clocks are separated to two parts and controlled by different
modules: ufs-mediatek and phy-ufs-mediatek.
If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control
is not balanced thus unbalanced control also happens to the clocks probed
by phy-ufs-mediatek module.
Fix this issue by:
- Promise usage of phy_power_on/off balanced
- Remove phy_power_on/off control in suspend/resume vops since both can be
handled in setup_clock vops only
Link: https://lore.kernel.org/r/20200601104646.15436-5-stanley.chu@mediatek.com
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
In current UFS driver design, hba->uic_link_state will not be changed after
link enters Hibern8 state by Auto-Hibern8 mechanism. In this case,
reference clock gating will be skipped unless special handling is
implemented in vendor's callbacks.
Support reference clock gating during Auto-Hibern8 period in MediaTek
Chipsets: If link state is already in Hibern8 while Auto-Hibern8 feature is
enabled, gate reference clock in setup_clocks callback.
Link: https://lore.kernel.org/r/20200129105251.12466-5-stanley.chu@mediatek.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Bean Huo <beanhuo@micron.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
