Commit Graph

8 Commits

Author SHA1 Message Date
Martin Blumenstingl
73106f75bf ARM: dts: meson: add the SDHC MMC controller
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller
IP which typically connects to an eMMC chip (because unlike the SDIO
controller the SDHC controller has an 8-bit bus interface).

On Meson8, Meson8b and Meson8m2 the clock inputs are all the same.
However, Meson8m2 seems to have an improved version of the SHDC
controller IP which doesn't require the driver to wait manually for a
flush of a DMA transfer. Thus every SoC has it's own compatible string
so if more difference are discovered they can be implemented.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
2020-07-13 11:58:15 -07:00
Martin Blumenstingl
c5d3d3cf00 ARM: dts: meson8m2: add resets for the power domain controller
The Meson8m2 SoCs has introduced additional reset lines for the VPU
compared to Meson8. Also it uses a slightly different VPU clock
frequency compared to Meson8 since it can now achieve 364MHz thanks to
the addition of the GP_PLL.
Add the reset lines, VPU clock configuration and update the compatible
string so the implementation differences can be managed.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-3-martin.blumenstingl@googlemail.com
2020-07-13 11:56:23 -07:00
Martin Blumenstingl
b632506c5a ARM: dts: meson: Add the Ethernet "timing-adjustment" clock
Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com
2020-05-19 16:18:58 -07:00
Martin Blumenstingl
f5a7382d6f ARM: dts: meson8m2: Use the Meson8m2 specific USB2 PHY compatible
Use the Meson8m2 specific USB2 PHY compatible string. The 3.10 vendor
kernel has at least one known difference between Meson8 and Meson8m2:
Meson8m2 sets the ACA_ENABLE bit while Meson8 doesn't.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200515202520.1487514-1-martin.blumenstingl@googlemail.com
2020-05-19 16:17:28 -07:00
Martin Blumenstingl
10256a4755 ARM: dts: meson8m2: update the offset of the canvas module
With the Meson8m2 SoC the canvas module was moved from offset 0x20
(Meson8) to offset 0x48 (same as on Meson8b). The offsets inside the
canvas module are identical.

Correct the offset so the driver uses the correct registers.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-05-22 18:18:09 -07:00
Martin Blumenstingl
c0ad99a2de ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible
The SAR ADC on Meson8m2 is slightly different compared to Meson8. The
ADC functionality is identical but the calibration of the internal
thermal sensor is different.

Use the Meson8m2 specific compatible so the temperature sensor is
calibrated correctly on boards using the Meson8m2 SoC.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:25 -08:00
Jerome Brunet
7e26335b1a ARM: dts: meson: consistently disable pin bias
On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.

As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.

The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.

There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.

This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-28 16:41:11 -08:00
Martin Blumenstingl
e592f6585c ARM: dts: meson: add support for the Meson8m2 SoC
This adds a meson8m2.dtsi which simply inherits meson8.dtsi as both SoCs
share most peripherals.
The known differences are:
- Meson8m2's hardware video decoder additionally supports H.265 decoding
- Meson8m2 has the same Gigabit MAC as Meson8b (instead of the 10/100M
  MAC that Meson8 uses)
- Meson8m2 uses the same watchdog register layout/bits as Meson8b (using
  the Meson8 watchdog compatible leads to an infinite hang when
  rebooting the machine)
- Meson8m2 uses the same SAR ADC register layout/bits as Meson8b.
  However, it uses the temperature sensor calibration formula (and
  registers) Meson8b which differ from Meson8. This however is currently
  not supported by the meson-saradc driver yet.
- the pin controller is mostly compatible with Meson8, Meson8m2 has
  an additional function on eight pins and removes the "VGA" function.
  So there's a total of 10 pins which are slightly changed, which is why
  there's a separate compatible for the pin controller
- a separate compatible for the clock controller is used because at
  least the Mali clock tree (not supported yet) is the same as on GXBB
  while Meson8 and Meson8b have a reduced/older version of the Mali
  clock tree.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-05-10 17:03:28 -07:00