Make the power management code under arch/arm/mach-shmobile/ use
names of power domains instead of pointers to domain objects for
adding devices to the domains. This will allow us to put the
domain objects into tables and register them all in one shot
going forward.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Magnus Damm <damm@opensource.se>
* renesas-sh7372:
ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
ARM: shmobile: Take cpuidle dependencies into account correctly
ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
ARM: shmobile: ap4evb: switch to using pm-rmobile API
ARM: shmobile: mackerel: switch to using pm-rmobile API
ARM: shmobile: sh7372: add pm-rmobile domain support
ARM: shmobile: sh7372 A3SM CPUIdle support
ARM: shmobile: Use INTCA with sh7372 A3SM power domain
ARM: shmobile: use common DMAEngine definitions on sh7372
ARM: shmobile: sh7372: remove unused sh7372_a3sp_init() on !CONFIG_PM
Now, all sh7372 platforms are switched over to use pm-rmobile base PM domain,
and no one is using original sh7372_pm_domain APIs.
We can remove these, switching has been fully completed.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch adds pm-rmobile common API base PM domain.
sh7372 CPU/platform will switch to using it from
original implementation
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch switch over to use common DMAEngine definitions,
and reduced a waste of code.
It is easy to understand if sh_dmae_pdata / sh_dmae_slave_config
settings are used defined value instead of direct value.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
chclr_write() will use (chan_reg + chclr_offset).
In sh7372 case, DMA1CHCLR is started from 0xfe008220,
and chan_reg is started from 0xfe008020 (= sh7372_dmae0_resources).
Thus, chclr_offset should be (0x220 - 0x20) instead of 0x220.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Simon Horman <horms@verge.net.au>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add generic DT board support for the sh7372 SoC V2.
SCIF serial ports and timers are kept as regular
platform devices. Other on-chip and on-board devices
should be configured via the device tree.
Tested on the mackerel board via kexec using a zImage
kernel with an appended dtb.
At this point there is no interrupt controller support
in place but such code will be added over time when
proper IRQ domain support has been added to INTC.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Pull more ARM updates from Russell King.
This got a fair number of conflicts with the <asm/system.h> split, but
also with some other sparse-irq and header file include cleanups. They
all looked pretty trivial, though.
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits)
ARM: fix Kconfig warning for HAVE_BPF_JIT
ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds
ARM: 7349/1: integrator: convert to sparse irqs
ARM: 7259/3: net: JIT compiler for packet filters
ARM: 7334/1: add jump label support
ARM: 7333/2: jump label: detect %c support for ARM
ARM: 7338/1: add support for early console output via semihosting
ARM: use set_current_blocked() and block_sigmask()
ARM: exec: remove redundant set_fs(USER_DS)
ARM: 7332/1: extract out code patch function from kprobes
ARM: 7331/1: extract out insn generation code from ftrace
ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format
ARM: 7351/1: ftrace: remove useless memory checks
ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path
ARM: Versatile Express: add NO_IOPORT
ARM: get rid of asm/irq.h in asm/prom.h
ARM: 7319/1: Print debug info for SIGBUS in user faults
ARM: 7318/1: gic: refactor irq_start assignment
ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop
ARM: 7315/1: perf: add support for the Cortex-A7 PMU
...
This branch contains a handful of updates of SoC base code that had
dependencies on other external trees that have now been merged:
* Support for the new EXYNOS5250 SoC from Samsung
* SMP and power domain support for Tegra3 from NVIDIA
* ux500 updates for exporting SoC information through sysfs
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: More SoC support updates" from Olof Johansson:
"This branch contains a handful of updates of SoC base code that had
dependencies on other external trees that have now been merged:
* Support for the new EXYNOS5250 SoC from Samsung
* SMP and power domain support for Tegra3 from NVIDIA
* ux500 updates for exporting SoC information through sysfs"
Fix up trivial merge conflicts as per Olof.
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits)
ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer
ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board
ARM: dts: add initial dts file for EXYNOS5250, SMDK5250
ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
ARM: EXYNOS: add support get_core_count() for EXYNOS5250
ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
ARM: EXYNOS: add interrupt definitions for EXYNOS5250
ARM: EXYNOS: add support for EXYNOS5250 SoC
ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
ARM: EXYNOS: add clock part for EXYNOS5250 SoC
ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
ARM: EXYNOS: to declare static for mach-exynos/common.c
ARM: EXYNOS: Add clkdev lookup entry for lcd clock
ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
ARM: tegra: support for secondary cores on Tegra30
ARM: tegra: support for Tegra30 CPU powerdomains
ARM: tegra: add support for Tegra30 powerdomains
ARM: tegra: export tegra_powergate_is_powered()
...
These are split out from the generic soc and driver updates because
there was a lot of conflicting work by multiple people. Marc Zyngier
worked on simplifying the "localtimer" interfaces, and some of the
platforms are touching the same code as they move to device tree
based booting.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: timer cleanup work" from Arnd Bergmann:
"These are split out from the generic soc and driver updates because
there was a lot of conflicting work by multiple people. Marc Zyngier
worked on simplifying the "localtimer" interfaces, and some of the
platforms are touching the same code as they move to device tree based
booting.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>"
* tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (61 commits)
ARM: tegra: select USB_ULPI if USB is selected
arm/tegra: pcie: fix return value of function
ARM: ux500: fix compilation after local timer rework
ARM: shmobile: remove additional __io() macro use
ARM: local timers: make the runtime registration interface mandatory
ARM: local timers: convert MSM to runtime registration interface
ARM: local timers: convert exynos to runtime registration interface
ARM: smp_twd: remove old local timer interface
ARM: imx6q: convert to twd_local_timer_register() interface
ARM: highbank: convert to twd_local_timer_register() interface
ARM: ux500: convert to twd_local_timer_register() interface
ARM: shmobile: convert to twd_local_timer_register() interface
ARM: tegra: convert to twd_local_timer_register() interface
ARM: plat-versatile: convert to twd_local_timer_register() interface
ARM: OMAP4: convert to twd_local_timer_register() interface
ARM: smp_twd: add device tree support
ARM: smp_twd: add runtime registration support
ARM: local timers: introduce a new registration interface
ARM: smp_twd: make local_timer_stop a symbol instead of a #define
ARM: mach-shmobile: default to no earlytimer
...
Conflicts:
arch/arm/mach-shmobile/board-ap4evb.c
This moves the addition of init_consistent_dma_size() from the board
files into the common sh7372_map_io() functions where all the other
contents of the board specific map_io calls have gone.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* pm-domains:
PM / shmobile: Make MTU2 driver use pm_genpd_dev_always_on()
PM / shmobile: Make CMT driver use pm_genpd_dev_always_on()
PM / shmobile: Make TMU driver use pm_genpd_dev_always_on()
PM / Domains: Introduce "always on" device flag
PM / Domains: Fix hibernation restore of devices, v2
PM / Domains: Fix handling of wakeup devices during system resume
Make the TMU clocksource driver mark its device as "always on"
using pm_genpd_dev_always_on() to protect it from surprise power
removals and make sh7372_add_standard_devices() add TMU devices on
sh7372 to the A4R power domain so that their "always on" flags
are taken into account as appropriate.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Tested-by: Simon Horman <horms@verge.net.au>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: stable@vger.kernel.org
Move the SoC specific timer code from AP4EVB and Mackerel
to sh7372 setup code. This makes is possible to share
the SoC specific timer code across boards and it also
removes the need for a board specific timer structure.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Update the sh7372 SoC and the AP4EVB and Mackerel boards to make use
of the functions sh7372_map_io() and sh7372_add_early_devices().
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Remove NR_IRQS and explicitly include mach/irqs.h as needed. shmobile
properly allocates irq_descs for each irqchip, so setting .nr_irqs for
each machine is not needed.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The sh7372 contains a power domain named A4S which in turn
contains power domains for both I/O Devices and CPU cores.
At this point only System wide Suspend-to-RAM is supported,
but the the hardware can also support CPUIdle. With more
efforts in the future CPUIdle can work with bot A4S and A3SM.
Tested on the sh7372 Mackerel board.
[rjw: Rebased on top of the current linux-pm tree.]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This change adds support for the sh7372 A4R power domain.
The sh7372 A4R hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.
One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This change adds support for the sh7372 A3SP power domain.
The sh7372 A3SP hardware power domain contains a
wide range of I/O devices. The list of I/O devices
include SCIF serial ports, DMA Engine hardware,
SD and MMC controller hardware, USB controllers
and I2C master controllers.
This patch adds the A3SP low level code which
powers the hardware power domain on and off. It
also ties in platform devices to the pm domain
support code.
It is worth noting that the serial console is
hooked up to SCIFA0 on most sh7372 boards, and
the SCIFA0 port is included in the A3SP hardware
power domain. For this reason we cannot output
debug messages from the low level power control
code in the case of A3SP.
QoS support is needed in drivers before we can
enable the A3SP power control on the fly.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Merge commit e8b364b88c
(PM / Clocks: Do not acquire a mutex under a spinlock) fixing
a regression in drivers/base/power/clock_ops.c.
Conflicts:
drivers/base/power/clock_ops.c
Instead of coding the undocumented dependencies between power domains
A3RV and A4LC on SH7372 directly into the low-level power up/down
routines, make A3RV be a subdomain of A4LC, which will cause the
same dependecies to hold.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Magnus Damm <damm@opensource.se>
Switch the sh7372 CPU support to use CMT2 instead
of CMT1 for system timer.
CMT1 is located in the A3SP power domain while CMT2
is located in the always-on power domain C5.
This improves our PM situation - with CMT2 as timer
we can power down A3SP and still access the timer.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add support for the sh7372 D4 power domain. This power domain
contains the Coresight-ETM hardware block.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A4MP power domain
and hook up the FSI/SPU2 device.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A3SG power domain. This domain contains
the SGX hardware block, but there is no open source driver available.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A3RI power domain. This domain contains
the ISP hardware block, but there is no driver available.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A3RV power domain and hook
up the VPU device.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
The AP4EVB board is also using a sh7372 SoC, so tie in
A4LC support on that board as well.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Export the following sh7372 multimedia hardware blocks
using UIO: VPU, VEU[0-3], JPU and SPU2[0-1]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add DMA slave IDs and slave definitions for MMCIF on sh7372.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds support for the two first channels of
the TMU0 timer block on sh7372. One channel is used
for clock event, the other for clock source.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Move SH-Mobile ARM systems over from the legacy
"clk" member of struct sh_timer_config to using
the device name and clkdev for clock matching.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch introduces sh7372_late_devices which
should include all regular processor specific
platform devices.
Early platform devices for console and timers
should be put on the sh7372_early_devices list,
all other devices should be on sh7372_late_devices.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Use evt2irq() for DMAC resources on sh7372.
This makes the code easier to read and also
allows adjusting the INTC base offset without
breaking platform data.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7372 can use DMA with the SCI serial driver. Add required slave IDs and slave
descriptors.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds DMA support for the sh7372 sh-mobile ARM core, using the shdma
dmaengine driver, and uses DMA for the SDHI SD-card controller on this SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The current SH7372 setup code registers 7 SCIF ports, which is wrong.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch updates the irq numbers on sh7372/AP4EVB
to make use of evt2irq() and intcs_evt2irq().
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch is V2 of clock framework tables/code for sh7372.
MSTP are included for KEYSC, SCIF, IIC, USB, SDHI and UIO.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh7372 chip has 2 INTC.
Then, I2C0 is connected to INTCS, and I2C1 is connected to INTCA.
Both of these has no GPIO settings.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
