This is a preparatory patch for moving irq_data struct members.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Link: http://lkml.kernel.org/r/20150713151626.713278346@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
It was already pointed out how to fix these cases before the offending
patches were merged, but unsurprisingly, that didn't happen. As this
change is entirely superfluous to begin with, simply shut things up by
casting everything away.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This ensures that the sense/prio lists are sorted at registration time,
enabling us to use a simple binary search for an optimized lookup
(something that had been on the TODO for some time).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
intc_set_affinity() updates the cpumask in place, so there's no need for
the upper layer to do this itself.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
It's possible to use IRQCHIP_SKIP_SET_WAKE to get the behaviour that
we're after, without having to bother with a dummy ->set_wake() callback
for the IRQ chip.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Enable IRQ_TYPE_EDGE_BOTH on all R/SH-Mobile ARM SoCs.
This hardware feature is supported by sh7367, sh7377,
sh7372 and sh73a0.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
R-Mobile SoCs such as sh73a0 include PINT blocks in INTC
that come with 2-bit IRQ trigger support. Add code to make
sure the bit width is checked so 4-bit only modes like for
instance EDGE_BOTH will fail for PINT.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
IRQ-capable GPIOs on sh7372 can be configured to produce interrupts on
both edges.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Clear the valid flag is in the INTC code.
Without this fix bit 7 of the sense register
is mistakenly set.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This splits up the sh intc core in to something more vaguely resembling
a subsystem. Most of the functionality was alread fairly well
compartmentalized, and there were only a handful of interdependencies
that needed to be resolved in the process.
This also serves as future-proofing for the genirq and sparseirq rework,
which will make some of the split out functionality wholly generic,
allowing things to be killed off in place with minimal migration pain.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
