Use the status tag to determine if there are new events in
tg3_interrupt_tagged(). We discussed about this a while ago with Grant
Grundler and DaveM. This scheme makes it unnecessary to clear the
updated bit in the status block when using tagged mode, and only
a simple comparison is needed to determine if there are new events.
The tp->lock around netif_rx_complete() and tg3_restart_ints() is also
removed. It is unnecessary with DaveM's new locking scheme.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Remove unnecessary status block accesses in tg3_msi(). Since MSI is
not shared, it is unnecessary to read the status block to determine if
there are any new events in the MSI handler. It is also unnecessary to
clear the updated bit in the status block.
Since the poll list is per-cpu, tg3_poll() will be scheduled to run on
the same CPU that received the MSI. Prefetches for the status block
and the next rx descriptors are added in tg3_msi() to improve their
access times when tg3_poll() runs.
In the non-MSI irq handlers, we need to check the status block because
interrupts may be shared. Only prefetches for the next rx descriptors
are added.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Improve ethtool loopback self test by adding PHY loopback to the
existing MAC loopback test.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Minor SerDes bug fixes for 5780S and nvram bug fixes for 5780 and
5752.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This is similar to Eric Dumazet's tx_lock patch for tg3 but takes it
one step further to eliminate the tx_lock in the tx_completion path
when the tx queue is not stopped.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Found a bug while reviewing the patches the second time.
The TG3_FLAG_TXD_MBOX_HWBUG flag is set after the register access
methods have been determined. This patch fixes it by moving it up before
the various access methods are assigned.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The register write to register 0x68 to restart interrupts is unnecessary
as the interrupt wasn't masked in that register by the irq handler. This
will save one register write in the fast path.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds the new workaround for 5703 A1/A2 if it is behind
certain ICH bridges. The workaround disables memory and uses config.
cycles only to access all registers. The 5702/03 chips can mistakenly
decode the special cycles from the ICH chipsets as memory write cycles,
causing corruption of register and memory space. Only certain ICH
bridges will drive special cycles with non-zero data during the address
phase which can fall within the 5703's address range. This is not an ICH
bug as the PCI spec allows non-zero address during special cycles.
However, only these ICH bridges are known to drive non-zero addresses
during special cycles.
The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh
because it is used in irq handler when using the indirect method to
disable interrupts.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds the mailbox read method and also adds an inline function
tw32_mailbox_f() for mailbox writes that require read flush.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds various dedicated register read/write methods for the
existing workarounds, including PCIX target workaround, write with read
flush, etc. The chips that require these workarounds will use these
dedicated access functions.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds the basic function pointers to do register accesses in
the fast path. This was suggested by David Miller. The idea is that
various register access methods for different hardware errata can easily
be implemented with these function pointers and performance will not be
degraded on chips that use normal register access methods.
The various register read write macros (e.g. tw32, tr32, tw32_mailbox)
are redefined to call the function pointers.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The tg3_abort_hw() call in tg3_test_loopback() is causing lockups on
some devices. tg3_abort_hw() disables the memory arbiter, causing
tg3_reset_hw() to hang when it tries to write the pre-reset signature.
tg3_abort_hw() should only be called after the pre-reset signature has
been written. This is all done in tg3_reset_hw() so the tg3_abort_hw()
call is unnecessary and can be removed.
[ Also bump driver version and release date. -DaveM ]
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
A problem was reported by Grant Grundler on an HP rx8620 using IOX
Core LAN partno(A7109-6) 5701 copper NIC. The tg3 driver mistakenly
detects this NIC as having a SerDes PHY and link does not come up as a
result.
The problem was caused by an incorrectly programmed eeprom that set the
NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit in the NIC_SRAM_DATA_CFG location.
This patch will override the NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit if a
valid PHY ID is read from the MII registers on older 570x chips where
the MII interface is not used on SerDes chips. On newer chips such as
the 5780 that use MII for both copper and SerDes, SerDes detection must
rely on the eeprom.
This patch will make the SerDes detection identical to versions 3.25 and
older.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Grant Grundler <iod00d@hp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Else on SMP systems it is possible for hotplug to execute,
invoke tg3_open(), and end up loading the uninitialized
PCI register save area into the card.
Signed-off-by: David S. Miller <davem@davemloft.net>
Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and
a timer function for parallel link detection. 5780S uses standard MII
registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on
older serdes chips.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Disallow jumbo TSO on 5780 due to hardware restrictions.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Consolidate all DMA watermark settings for standard and jumbo frames on
all chips in tg3_init_bufmgr_config() and add new settings for 5780.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add a new rx_pkt_buf_sz to the tg3 structure to support variable buffer
sizes on the standard ring.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add basic jumbo frames support for 5780. This chip supports jumbo frames
on the standard receive ring without the jumbo ring. The
TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to
indicate using the jumbo ring on 5704 and older chips. A new
TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support
with or without the jumbo ring.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add 5780 PCI IDs, chip IDs, and other basic support.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for ethtool -C with verification of user parameters.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
1. Move tp->irq_sync = 0 to before the interrupt mailbox IO in
tg3_enable_ints() so that the interrupt handler will always see
irq_sync == 0 when interrupts are enabled.
2. Remove the tg3_enable_ints() call in tg3_reset_hw(). Interrupts are
always enabled explicitly or through tg3_netif_start(). This is to
prevent interrupts being enabled while poll is disabled.
3. Update trans_start with jiffies in tg3_netif_stop() to prevent false
NETDEV WATCHDOG.
4. Pass in the proper irq_sync parameter to tg3_full_lock() depending on
netif_running() in some of the ethtool set calls.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Move all driver spinlocks to be taken at sw IRQ
context only.
This fixes the skb_copy() we were doing with hw
IRQs disabled (which is illegal and triggers a
BUG() with HIGHMEM enabled). It also simplifies
the locking all over the driver tremendously.
We accomplish this feat by creating a special
sequence to synchronize with the hw IRQ handler
using a binary state and synchronize_irq().
This idea is from Herbert Xu.
Thanks to Michael Chan for helping to track down
all of the race conditions in initial versions
of this code.
Signed-off-by: David S. Miller <davem@davemloft.net>
There must be a rmb() between reading the status block tag
and calling tg3_has_work(). This was missing in tg3_mis()
and tg3_interrupt_tagged(). tg3_poll() got it right.
Also, SD_STATUS_UPDATED must be cleared in the status block
right before we call tg3_has_work(). Only tg3_poll() got this
wrong.
Based upon patches and commentary from Grant Grundler and
Michael Chan.
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix 5700/5701 DMA write corruption on Apple G4 by detecting the Apple
UniNorth PCI 1.5 chipset and adjusting the DMA write boundary to 16. DMA
test fails to detect the problem with this chipset.
Thanks to Manuel Perez Ayala for reporting the problem and helping to
debug it.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
On some 5701 devices with older bootcode, the LED configuration bits in
SRAM may be invalid with value zero. The fix is to check for invalid
bits (0) and default to PHY 1 mode. Incorrect LED mode will lead to
error in programming the PHY.
Thanks to Grant Grundler for debugging the problem.
>From Grant:
| In May, 2004, tg3 v3.4 changed how MAC_LED_CTRL (0x40c) was getting
| programmed and how to determine what to program into LED_CTRL. The new
| code trusted NIC_SRAM_DATA_CFG (0x00000b58) to indicate what to write
| to LED_CTRL and MII EXT_CTRL registers. On "IOX Core Lan", SRAM was
| saying MODE_MAC (0x0) and that doesn't work.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add tg3_nvram_lock() and tg3_nvram_unlock() calls around tg3_halt_cpu().
It is possible that the bootcode may be loading code from nvram during
this call and stopping the cpu without getting the lock may cause
uncompleted nvram data to be left in the nvram data register. Subsequent
calls to read/write nvram data will fail.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This test uses the previously added tg3_test_interrupt() to perform the
test.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The test will loopback one packet in MAC loopback mode and verify the
packet data.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add a reset kind parameter to tg3_halt() so that the RESET_KIND_SUSPEND
parameter can be passed to tg3_halt() before doing offline tests.
All other calls to tg3_halt() will use the RESET_KIND_SHUTDOWN
parameter.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add 0x1601 as 5752M, it's a 5752 but for mobile PCs.
Stolen from Broadcom bcm5700-8.1.55 driver.
Someone forgot to add it to tg3 ;-)
Signed-off-by: David S. Miller <davem@davemloft.net>
