- Drop the dependency on PCI, as this is implied by the dependency on
PCI_MSI_IRQ_DOMAIN,
- Drop the dependencies on OF and ARM64, as the driver compiles fine
without OF and/or on other architectures,
- The Freescale Layerscape PCIe Gen4 controller is present only on
Freescale Layerscape SoCs. Hence depend on ARCH_LAYERSCAPE, to
prevent asking the user about this driver when configuring a kernel
without Freescale Layerscape support, unless compile-testing.
Link: https://lore.kernel.org/r/20210208142301.413582-1-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
In config PCIE_TEGRA194_EP the mode incorrectly is referred to as
host mode. Fix it.
Link: https://lore.kernel.org/r/20201231032539.22322-1-wesley.sheng@amd.com
Signed-off-by: Wesley Sheng <wesley.sheng@amd.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Acked-by: Vidya Sagar <vidyas@nvidia.com>
Fix to return negative error code -ENODEV from the unsupported revision
error handling case instead of 0, as done elsewhere in this function.
Link: https://lore.kernel.org/r/20210308135619.19133-1-weiyongjun1@huawei.com
Fixes: 0cdfaceb98 ("PCI: brcmstb: support BCM4908 with external PERST# signal controller")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Both TI's AM65x (K3) and TI's K2 PCIe driver are implemented in
pci-keystone. However Only K2 PCIe driver should use it's own pci_ops
for configuration space accesses. But commit 10a797c6e5
("PCI: dwc: keystone: Use pci_ops for config space accessors") used
custom pci_ops for both AM65x and K2. This breaks configuration space
access for AM65x platform. Fix it here.
Link: https://lore.kernel.org/r/20210317131518.11040-1-kishon@ti.com
Fixes: 10a797c6e5 ("PCI: dwc: keystone: Use pci_ops for config space accessors")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Cc: <stable@vger.kernel.org> # v5.10
There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.
This change is as per suggestions from Coccinelle, e.g.,
drivers/pci/controller/pcie-microchip-host.c:1027:2-9: line 1027 is
redundant because platform_get_irq() already prints an error
Related commit caecb05c80 ("PCI: Remove dev_err() when handing an
error from platform_get_irq()").
Link: https://lore.kernel.org/r/20210310131913.2802385-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
The sparse tool complains as follows:
drivers/pci/controller/pcie-microchip-host.c:304:18: warning:
symbol 'pcie_event_to_event' was not declared. Should it be static?
drivers/pci/controller/pcie-microchip-host.c:310:18: warning:
symbol 'sec_error_to_event' was not declared. Should it be static?
drivers/pci/controller/pcie-microchip-host.c:317:18: warning:
symbol 'ded_error_to_event' was not declared. Should it be static?
drivers/pci/controller/pcie-microchip-host.c:324:18: warning:
symbol 'local_status_to_event' was not declared. Should it be static?
Those symbols are not used outside of pcie-microchip-host.c, so this
commit marks them static.
Link: https://lore.kernel.org/r/20210308094842.3588847-1-weiyongjun1@huawei.com
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
IRQ domain alloc function should return zero on success. Non-zero value
indicates failure.
Link: https://lore.kernel.org/r/20210303142202.25780-1-pali@kernel.org
Fixes: fc54bae288 ("PCI: iproc: Allow allocation of multiple MSIs")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Acked-by: Ray Jui <ray.jui@broadcom.com>
Acked-by: Marc Zyngier <maz@kernel.org>
VMD will retransmit child device MSI-X using its own MSI-X table and
requester-id. This limits the number of MSI-X available to the whole
child device domain to the number of VMD MSI-X interrupts.
Some VMD devices have a mode where this remapping can be disabled,
allowing child device interrupts to bypass processing with the VMD MSI-X
domain interrupt handler and going straight the child device interrupt
handler, allowing for better performance and scaling. The requester-id
still gets changed to the VMD endpoint's requester-id, and the interrupt
remapping handlers have been updated to properly set IRTE for child
device interrupts to the VMD endpoint's context.
Some VMD platforms have existing production BIOS which rely on MSI-X
remapping and won't explicitly program the MSI-X remapping bit. This
re-enables MSI-X remapping on unload.
Link: https://lore.kernel.org/r/20210210161315.316097-3-jonathan.derrick@intel.com
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Acked-by: Joerg Roedel <jroedel@suse.de>
The only usage of them is to assign their address to the 'ops' field in
the pcie_port and the dw_pcie_ep structs, both which are pointers to
const. Make them const to allow the compiler to put them in read-only
memory.
Link: https://lore.kernel.org/r/20210207221604.48910-1-rikard.falkeborn@gmail.com
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
The hv_compose_msi_msg() callback in irq_chip::irq_compose_msi_msg is
invoked via irq_chip_compose_msi_msg(), which itself is always invoked from
atomic contexts from the guts of the interrupt core code.
There is no way to change this w/o rewriting the whole driver, so use
tasklet_disable_in_atomic() which allows to make tasklet_disable()
sleepable once the remaining atomic users are addressed.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Wei Liu <wei.liu@kernel.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210309084242.516519290@linutronix.de
There are harmless warnings when compile testing the kernel with
CONFIG_TRIM_UNUSED_KSYMS:
drivers/pci/controller/dwc/pcie-al.o: no symbols
drivers/pci/controller/pci-thunder-ecam.o: no symbols
drivers/pci/controller/pci-thunder-pem.o: no symbols
The problem here is that the host drivers get built even when the
configuration symbols are all disabled, as they pretend to not be drivers
but are silently enabled because of the promise that ACPI-based systems
need no drivers.
Add back the normal symbols to have these drivers built, and change the
logic to otherwise only build them when both CONFIG_PCI_QUIRKS and
CONFIG_ACPI are enabled.
As a side-effect, this enables compile-testing the drivers on other
architectures, which in turn needs the acpi_get_rc_resources() function to
be defined.
Link: https://lore.kernel.org/r/20210308152501.2135937-3-arnd@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Robert Richter <rric@kernel.org>
Compile-testing these drivers is currently broken. Enabling it causes a
couple of build failures though:
drivers/pci/controller/pci-thunder-ecam.c:119:30: error: shift count >= width of type [-Werror,-Wshift-count-overflow]
drivers/pci/controller/pci-thunder-pem.c:54:2: error: implicit declaration of function 'writeq' [-Werror,-Wimplicit-function-declaration]
drivers/pci/controller/pci-thunder-pem.c:392:8: error: implicit declaration of function 'acpi_get_rc_resources' [-Werror,-Wimplicit-function-declaration]
Fix them with the obvious one-line changes.
Link: https://lore.kernel.org/r/20210308152501.2135937-2-arnd@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Robert Richter <rric@kernel.org>
Compile-testing this driver without ECAM support results in a link failure:
ld.lld: error: undefined symbol: pci_ecam_map_bus
>>> referenced by pcie-al.c
>>> pci/controller/dwc/pcie-al.o:(al_pcie_map_bus) in archive drivers/built-in.a
Select CONFIG_ECAM like the other drivers do.
Link: https://lore.kernel.org/r/20210308152501.2135937-1-arnd@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
After updating pci-dra7xx driver to probe with ti-sysc and genpd, I
noticed that dra7xx_pcie_probe() would not run if a power-domains property
was configured for the interconnect target module.
Turns out that module_platform_driver_probe uses platform_driver_probe(),
while builtin_platform_driver uses platform_driver_register().
Only platform_driver_register() works for deferred probe as noted in the
comments for __platform_driver_probe() in drivers/base/platform.c with a
line saying "Note that this is incompatible with deferred probing".
With module_platform_driver_probe, we have platform_driver_probe() produce
-ENODEV error at device_initcall() level, and no further attempts are done.
Let's fix this by using module_platform_driver instead.
Note this is not an issue currently as we probe devices with simple-bus,
and only is needed as we start probing the device with ti-sysc, or when
probed with simple-pm-bus.
Note that we must now also remove __init for probe related functions to
avoid a section mismatch warning.
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Merge tag 'pci-v5.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Remove unnecessary locking around _OSC (Bjorn Helgaas)
- Clarify message about _OSC failure (Bjorn Helgaas)
- Remove notification of PCIe bandwidth changes (Bjorn Helgaas)
- Tidy checking of syscall user config accessors (Heiner Kallweit)
Resource management:
- Decline to resize resources if boot config must be preserved (Ard
Biesheuvel)
- Fix pci_register_io_range() memory leak (Geert Uytterhoeven)
Error handling (Keith Busch):
- Clear error status from the correct device
- Retain error recovery status so drivers can use it after reset
- Log the type of Port (Root or Switch Downstream) that we reset
- Always request a reset for Downstream Ports in frozen state
Endpoint framework and NTB (Kishon Vijay Abraham I):
- Make *_get_first_free_bar() take into account 64 bit BAR
- Add helper API to get the 'next' unreserved BAR
- Make *_free_bar() return error codes on failure
- Remove unused pci_epf_match_device()
- Add support to associate secondary EPC with EPF
- Add support in configfs to associate two EPCs with EPF
- Add pci_epc_ops to map MSI IRQ
- Add pci_epf_ops to expose function-specific attrs
- Allow user to create sub-directory of 'EPF Device' directory
- Implement ->msi_map_irq() ops for cadence
- Configure LM_EP_FUNC_CFG based on epc->function_num_map for cadence
- Add EP function driver to provide NTB functionality
- Add support for EPF PCI Non-Transparent Bridge
- Add specification for PCI NTB function device
- Add PCI endpoint NTB function user guide
- Add configfs binding documentation for pci-ntb endpoint function
Broadcom STB PCIe controller driver:
- Add support for BCM4908 and external PERST# signal controller
(Rafał Miłecki)
Cadence PCIe controller driver:
- Retrain Link to work around Gen2 training defect (Nadeem Athani)
- Fix merge botch in cdns_pcie_host_map_dma_ranges() (Krzysztof
Wilczyński)
Freescale Layerscape PCIe controller driver:
- Add LX2160A rev2 EP mode support (Hou Zhiqiang)
- Convert to builtin_platform_driver() (Michael Walle)
MediaTek PCIe controller driver:
- Fix OF node reference leak (Krzysztof Wilczyński)
Microchip PolarFlare PCIe controller driver:
- Add Microchip PolarFire PCIe controller driver (Daire McNamara)
Qualcomm PCIe controller driver:
- Use PHY_REFCLK_USE_PAD only for ipq8064 (Ansuel Smith)
- Add support for ddrss_sf_tbu clock for sm8250 (Dmitry Baryshkov)
Renesas R-Car PCIe controller driver:
- Drop PCIE_RCAR config option (Lad Prabhakar)
- Always allocate MSI addresses in 32bit space (Marek Vasut)
Rockchip PCIe controller driver:
- Add FriendlyARM NanoPi M4B DT binding (Chen-Yu Tsai)
- Make 'ep-gpios' DT property optional (Chen-Yu Tsai)
Synopsys DesignWare PCIe controller driver:
- Work around ECRC configuration hardware defect (Vidya Sagar)
- Drop support for config space in DT 'ranges' (Rob Herring)
- Change size to u64 for EP outbound iATU (Shradha Todi)
- Add upper limit address for outbound iATU (Shradha Todi)
- Make dw_pcie ops optional (Jisheng Zhang)
- Remove unnecessary dw_pcie_ops from al driver (Jisheng Zhang)
Xilinx Versal CPM PCIe controller driver:
- Fix OF node reference leak (Pan Bian)
Miscellaneous:
- Remove tango host controller driver (Arnd Bergmann)
- Remove IRQ handler & data together (altera-msi, brcmstb, dwc)
(Martin Kaiser)
- Fix xgene-msi race in installing chained IRQ handler (Martin
Kaiser)
- Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy (Junhao He)
- Fix pci-bridge-emul array overruns (Russell King)
- Remove obsolete uses of WARN_ON(in_interrupt()) (Sebastian Andrzej
Siewior)"
* tag 'pci-v5.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (69 commits)
PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064
PCI: qcom: Add support for ddrss_sf_tbu clock
dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250
PCI: al: Remove useless dw_pcie_ops
PCI: dwc: Don't assume the ops in dw_pcie always exist
PCI: dwc: Add upper limit address for outbound iATU
PCI: dwc: Change size to u64 for EP outbound iATU
PCI: dwc: Drop support for config space in 'ranges'
PCI: layerscape: Convert to builtin_platform_driver()
PCI: layerscape: Add LX2160A rev2 EP mode support
dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible strings
PCI: dwc: Work around ECRC configuration issue
PCI/portdrv: Report reset for frozen channel
PCI/AER: Specify the type of Port that was reset
PCI/ERR: Retain status from error notification
PCI/AER: Clear AER status from Root Port when resetting Downstream Port
PCI/ERR: Clear status of the reporting device
dt-bindings: arm: rockchip: Add FriendlyARM NanoPi M4B
PCI: rockchip: Make 'ep-gpios' DT property optional
Documentation: PCI: Add PCI endpoint NTB function user guide
...
- Remove IRQ handler & data together for altera, brcmstb, dwc (Martin
Kaiser)
- Fix xgene race in installing chained IRQ handler (Martin Kaiser)
- Drop PCIE_RCAR config option (replaced by PCIE_RCAR_HOST) (Lad Prabhakar)
- Fix xgene comment about CRS vs CRS SV (Bjorn Helgaas)
* remotes/lorenzo/pci/misc:
PCI: hv: Fix typo
PCI: xgene: Fix CRS SV comment
PCI: brcmstb: Remove chained IRQ handler and data in one go
PCI: Drop PCIE_RCAR config option
PCI: xgene-msi: Fix race in installing chained irq handler
PCI: dwc: Remove IRQ handler and data in one go
PCI: altera-msi: Remove IRQ handler and data in one go
- Always allocate rcar MSI addresses in 32-bit space so legacy devices
without 64-bit MSI support can use MSI (Marek Vasut)
* remotes/lorenzo/pci/rcar:
PCI: rcar: Always allocate MSI addresses in 32bit space
- Add support for SM8250 PCIe SF TBU clock (Dmitry Baryshkov)
- Use PHY_REFCLK_USE_PAD only for qcom ipq8064 (Ansuel Smith)
* pci/qcom:
PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064
PCI: qcom: Add support for ddrss_sf_tbu clock
dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250
- Account for 64-bit BARs in pci_epc_get_first_free_bar() (Kishon Vijay
Abraham I)
- Add pci_epc_get_next_free_bar() helper (Kishon Vijay Abraham I)
- Return error codes on failure of endpoint BAR interfaces (Kishon Vijay
Abraham I)
- Remove unused pci_epf_match_device() (Kishon Vijay Abraham I)
- Add support for secondary endpoint controller to prepare for NTB endpoint
functionality (Kishon Vijay Abraham I)
- Add configfs support for secondary endpoint controller (Kishon Vijay
Abraham I)
- Add MSI address mapping ops for NTB doorbell support (Kishon Vijay
Abraham I)
- Add ops for endpoint function-specific attributes (Kishon Vijay Abraham
I)
- Allow configfs subdirectory for endpoint function configuration (Kishon
Vijay Abraham I)
- Implement cadence MSI address mapping ops (Kishon Vijay Abraham I)
- Configure cadence LM_EP_FUNC_CFG based on epc->function_num_map (Kishon
Vijay Abraham I)
- Add endpoint-side driver to provide NTB functionality (Kishon Vijay
Abraham I)
- Add host-side driver for generic EPF NTB functionality (Kishon Vijay
Abraham I)
- Document NTB endpoint functionality (Kishon Vijay Abraham I)
* pci/ntb:
Documentation: PCI: Add PCI endpoint NTB function user guide
Documentation: PCI: Add configfs binding documentation for pci-ntb endpoint function
NTB: Add support for EPF PCI Non-Transparent Bridge
PCI: Add TI J721E device to PCI IDs
PCI: endpoint: Add EP function driver to provide NTB functionality
PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_map
PCI: cadence: Implement ->msi_map_irq() ops
PCI: endpoint: Allow user to create sub-directory of 'EPF Device' directory
PCI: endpoint: Add pci_epf_ops to expose function-specific attrs
PCI: endpoint: Add pci_epc_ops to map MSI IRQ
PCI: endpoint: Add support in configfs to associate two EPCs with EPF
PCI: endpoint: Add support to associate secondary EPC with EPF
PCI: endpoint: Remove unused pci_epf_match_device()
PCI: endpoint: Make *_free_bar() to return error codes on failure
PCI: endpoint: Add helper API to get the 'next' unreserved BAR
PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR
Documentation: PCI: Add specification for the PCI NTB function device
- Always set DesignWare "TLP Digest" bit so generic code can enable ECRC
via the AER Capability (Vidya Sagar)
- Drop support for config space in DT 'ranges' (Rob Herring)
- Increase width of outbound iATU size to u64 (Shradha Todi)
- Add upper limit address for outbound iATU (Shradha Todi)
- Allow dwc-based drivers that don't override any default ops (Jisheng
Zhang)
- Drop unnecessary dw_pcie_ops from the al driver (Jisheng Zhang)
* pci/dwc:
PCI: al: Remove useless dw_pcie_ops
PCI: dwc: Don't assume the ops in dw_pcie always exist
PCI: dwc: Add upper limit address for outbound iATU
PCI: dwc: Change size to u64 for EP outbound iATU
PCI: dwc: Drop support for config space in 'ranges'
PCI: dwc: Work around ECRC configuration issue
- Retrain Link to work around Gen2 training defect (Nadeem Athani)
* remotes/lorenzo/pci/cadence:
PCI: cadence: Retrain Link to work around Gen2 training defect
- Add support for BCM4908 with external PERST# signal controller (Rafał
Miłecki)
* remotes/lorenzo/pci/brcmstb:
PCI: brcmstb: support BCM4908 with external PERST# signal controller
dt-bindings: PCI: brcmstb: add BCM4908 binding
The use of PHY_REFCLK_USE_PAD introduced a regression for apq8064 devices.
It was tested that while apq doesn't require the padding, ipq SoC must use
it or the kernel hangs on boot.
Link: https://lore.kernel.org/r/20201019165555.8269-1-ansuelsmth@gmail.com
Fixes: de3c4bf648 ("PCI: qcom: Add support for tx term offset for rev 2.1.0")
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: stable@vger.kernel.org # v4.19+
We have removed the assumption that dw_pcie_ops always exists in the dwc
core driver, so we can remove the useless dw_pcie_ops now.
Link: https://lore.kernel.org/r/20210128144324.2fa8577c@xhacker.debian
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jonathan Chocron <jonnyc@amazon.com>
Some dwc-based device drivers, especially host-only drivers, may work well
with the default read_dbi/write_dbi/link_up implementations in
pcie-designware.c, so remove the assumption that every driver implements
them to simplify those drivers.
Link: https://lore.kernel.org/r/20210128144258.10329aa4@xhacker.debian
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The size parameter is unsigned long type which can accept size > 4GB. In
that case, the upper limit address must be programmed. Add support to
program the upper limit address and set INCREASE_REGION_SIZE in case size >
4GB.
Link: https://lore.kernel.org/r/1612250918-19610-1-git-send-email-shradha.t@samsung.com
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Since outbound iATU permits size to be greater than 4GB for which the
support is also available, allow EP function to send u64 size instead of
truncating to u32.
Link: https://lore.kernel.org/r/1609929900-19082-1-git-send-email-shradha.t@samsung.com
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Since commit a0fd361db8 ("PCI: dwc: Move "dbi", "dbi2", and
"addr_space" resource setup into common code"), the code
setting dbi_base when the config space is defined in 'ranges' property
instead of 'reg' is dead code as dbi_base is never NULL.
Rather than fix this, let's just drop the code. Using ranges has been
deprecated since 2014. The only platforms using this were exynos5440,
i.MX6 and Spear13xx. Exynos5440 is dead and has been removed. i.MX6 and
Spear13xx had PCIe support added just before this was deprecated and
were fixed within a kernel release or 2.
Link: https://lore.kernel.org/r/20201215194149.86831-1-robh@kernel.org
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
fw_devlink will defer the probe until all suppliers are ready. We can't
use builtin_platform_driver_probe() because it doesn't retry after probe
deferral. Convert it to builtin_platform_driver().
Link: https://lore.kernel.org/r/20210120105246.23218-1-michael@walle.cc
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe
controller is integrated with different stride between PFs' register
address.
Link: https://lore.kernel.org/r/20201026051448.1913-2-Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a.
[bhelgaas: fix typos/grammar errors]
Link: https://lore.kernel.org/r/20201230165723.673-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is
an optional property. And indeed there are boards that don't require it.
Make the driver follow the binding by using devm_gpiod_get_optional()
instead of devm_gpiod_get().
[bhelgaas: tidy whitespace]
Link: https://lore.kernel.org/r/20210121162321.4538-2-wens@kernel.org
Fixes: e77f847df5 ("PCI: rockchip: Add Rockchip PCIe controller support")
Fixes: 956cd99b35 ("PCI: rockchip: Separate common code from RC driver")
Fixes: 964bac9455 ("PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The number of functions supported by the endpoint controller is configured
in LM_EP_FUNC_CFG based on func_no member of struct pci_epf. Now that an
endpoint function can be associated with two endpoint controllers (primary
and secondary), just using func_no will not suffice as that will take into
account only if the endpoint controller is associated with the primary
interface of endpoint function. Instead use epc->function_num_map which
will already have the configured functions information (irrespective of
whether the endpoint controller is associated with primary or secondary
interface).
Link: https://lore.kernel.org/r/20210201195809.7342-13-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Tom Joseph <tjoseph@cadence.com>
Implement ->msi_map_irq() ops in order to map physical address to MSI
address and return MSI data.
Link: https://lore.kernel.org/r/20210201195809.7342-12-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Tom Joseph <tjoseph@cadence.com>
Add support for the Microchip PolarFire PCIe controller when configured in
host (Root Complex) mode.
[bhelgaas: wrap lines to fit in 80 columns, fix trivial style issues]
Link: https://lore.kernel.org/r/20210125162934.5335-4-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
[lorenzo.pieralisi@arm.com: minor comments tweak]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Many drivers can now use pci_host_common_probe() directly.
Their hardware window setup can be moved from their 'custom' probe
functions to individual driver init functions.
Link: https://lore.kernel.org/r/20210125162934.5335-2-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Function cdns_pcie_host_map_dma_ranges() iterates over a PCIe host bridge
DMA ranges using the resource_list_for_each_entry() iterator, returning an
error if cdns_pcie_host_bar_config() fails.
49e427e6bd ("Merge branch 'pci/host-probe-refactor'") botched a merge so
it *always* returned after the first DMA range, even if no error occurred.
Fix the error checking so we return early only when an error occurs.
[bhelgaas: commit log]
Fixes: 49e427e6bd ("Merge branch 'pci/host-probe-refactor'")
Link: https://lore.kernel.org/r/20210216205935.3112661-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
We will soon use the same structure to handle IO-APIC interrupts as
well. Introduce an enum to identify the source and a data structure for
IO-APIC RTE.
While at it, update pci-hyperv.c to use the enum.
No functional change.
Signed-off-by: Wei Liu <wei.liu@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20210203150435.27941-13-wei.liu@kernel.org
Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
Link: https://lore.kernel.org/r/20210209144622.26683-3-nadeem@cadence.com
Signed-off-by: Nadeem Athani <nadeem@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Configuration Request Retry Status ("CRS") must be supported by all PCIe
devices. CRS Software Visibility is an optional feature that enables a
Root Port to make CRS visible to software by returning a special data value
to complete a config read.
Clarify a comment to say that it is "CRS SV", not "CRS", that can be
enabled.
Link: https://lore.kernel.org/r/20210126213503.2922848-1-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
The for_each_available_child_of_node helper internally makes use of the
of_get_next_available_child() which performs an of_node_get() on each
iteration when searching for next available child node.
Should an available child node be found, then it would return a device
node pointer with reference count incremented, thus early return from
the middle of the loop requires an explicit of_node_put() to prevent
reference count leak.
To stop the reference leak, explicitly call of_node_put() before
returning after an error occurred.
Link: https://lore.kernel.org/r/20210120184810.3068794-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Also drop the reference count of the node on error path.
Link: https://lore.kernel.org/r/20210120143745.699-1-bianpan2016@163.com
Fixes: 508f610648 ("PCI: xilinx-cpm: Add Versal CPM Root Port driver")
Signed-off-by: Pan Bian <bianpan2016@163.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
The tango platform is getting removed, so the driver is no
longer needed.
Link: https://lore.kernel.org/r/20210120150800.1650898-1-arnd@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Mans Rullgard <mans@mansr.com>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Mans Rullgard <mans@mansr.com>
Call irq_set_chained_handler_and_data() to clear the chained handler
and the handler's data under irq_desc->lock.
See also 2cf5a03cb2 ("PCI/keystone: Fix race in installing chained
IRQ handler").
Link: https://lore.kernel.org/r/20210115211532.19837-1-martin@kaiser.cx
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
All the defconfig files have replaced PCIE_RCAR config option with
PCIE_RCAR_HOST config option which built the same driver, so we can
now safely drop PCIE_RCAR config option.
Link: https://lore.kernel.org/r/20201229170848.18482-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
BCM4908 uses external MISC block for controlling PERST# signal. Use it
as a reset controller.
Link: https://lore.kernel.org/r/20201210180421.7230-3-zajec5@gmail.com
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().
See also 2cf5a03cb2 ("PCI/keystone: Fix race in installing chained IRQ
handler").
Based on the mail discussion, it seems ok to drop the error handling.
Link: https://lore.kernel.org/r/20210115212435.19940-3-martin@kaiser.cx
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Call irq_set_chained_handler_and_data() to clear the chained handler
and the handler's data under irq_desc->lock.
See also 2cf5a03cb2 ("PCI/keystone: Fix race in installing chained
IRQ handler").
Link: https://lore.kernel.org/r/20210115212435.19940-2-martin@kaiser.cx
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Call irq_set_chained_handler_and_data() to clear the chained handler
and the handler's data under irq_desc->lock.
See also 2cf5a03cb2 ("PCI/keystone: Fix race in installing chained
IRQ handler").
Link: https://lore.kernel.org/r/20210115212435.19940-1-martin@kaiser.cx
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This fixes MSI operation on legacy PCI cards, which cannot issue 64bit MSIs.
The R-Car controller only has one MSI trigger address instead of two, one
for 64bit and one for 32bit MSI, set the address to 32bit PCIe space so that
legacy PCI cards can also trigger MSIs.
Link: https://lore.kernel.org/r/20201016120431.7062-1-marek.vasut@gmail.com
Fixes: 290c1fb358 ("PCI: rcar: Add MSI support for PCIe")
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: linux-renesas-soc@vger.kernel.org
Commit 660c486590 ("PCI: dwc: Set 32-bit DMA mask for MSI target address
allocation") added dma_mask_set() call to explicitly set 32-bit DMA mask
for MSI message mapping, but for now it throws a warning on ret == 0, while
dma_set_mask() returns 0 in case of success.
Fix this by inverting the condition.
[bhelgaas: join string to make it greppable]
Fixes: 660c486590 ("PCI: dwc: Set 32-bit DMA mask for MSI target address allocation")
Link: https://lore.kernel.org/r/20201222150708.67983-1-alobakin@pm.me
Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Commit b9ac0f9dc8 ("PCI: dwc: Move dw_pcie_setup_rc() to DWC common
code") broke enumeration of downstream devices on Tegra:
In non-working case (next-20201211):
0001:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad2 (rev a1)
0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13)
0005:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad0 (rev a1)
In working case (v5.10-rc7):
0001:00:00.0 PCI bridge: Molex Incorporated Device 1ad2 (rev a1)
0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13)
0005:00:00.0 PCI bridge: Molex Incorporated Device 1ad0 (rev a1)
0005:01:00.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab)
0005:02:02.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab)
0005:03:00.0 USB controller: PLX Technology, Inc. Device 3380 (rev ab)
The problem seems to be dw_pcie_setup_rc() is now called twice before and
after the link up handling. The fix is to move Tegra's link up handling to
.start_link() function like other DWC drivers. Tegra is a bit more
complicated than others as it re-inits the whole DWC controller to retry
the link. With this, the initialization ordering is restored to match the
prior sequence.
Fixes: b9ac0f9dc8 ("PCI: dwc: Move dw_pcie_setup_rc() to DWC common code")
Link: https://lore.kernel.org/r/20201218143905.1614098-1-robh@kernel.org
Reported-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Tested-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Vidya Sagar <vidyas@nvidia.com>
accesses, inefficient and disfunctional code. The goal is to remove the
export of irq_to_desc() to prevent these things from creeping up again.
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Merge tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"This is the second attempt after the first one failed miserably and
got zapped to unblock the rest of the interrupt related patches.
A treewide cleanup of interrupt descriptor (ab)use with all sorts of
racy accesses, inefficient and disfunctional code. The goal is to
remove the export of irq_to_desc() to prevent these things from
creeping up again"
* tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (30 commits)
genirq: Restrict export of irq_to_desc()
xen/events: Implement irq distribution
xen/events: Reduce irq_info:: Spurious_cnt storage size
xen/events: Only force affinity mask for percpu interrupts
xen/events: Use immediate affinity setting
xen/events: Remove disfunct affinity spreading
xen/events: Remove unused bind_evtchn_to_irq_lateeoi()
net/mlx5: Use effective interrupt affinity
net/mlx5: Replace irq_to_desc() abuse
net/mlx4: Use effective interrupt affinity
net/mlx4: Replace irq_to_desc() abuse
PCI: mobiveil: Use irq_data_get_irq_chip_data()
PCI: xilinx-nwl: Use irq_data_get_irq_chip_data()
NTB/msi: Use irq_has_action()
mfd: ab8500-debugfs: Remove the racy fiddling with irq_desc
pinctrl: nomadik: Use irq_has_action()
drm/i915/pmu: Replace open coded kstat_irqs() copy
drm/i915/lpe_audio: Remove pointless irq_to_desc() usage
s390/irq: Use irq_desc_kstat_cpu() in show_msi_interrupt()
parisc/irq: Use irq_desc_kstat_cpu() in show_interrupts()
...
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Merge tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Decode PCIe 64 GT/s link speed (Gustavo Pimentel)
- Remove unused HAVE_PCI_SET_MWI (Heiner Kallweit)
- Reduce pci_set_cacheline_size() message to debug level (Heiner
Kallweit)
- Fix pci_slot_release() NULL pointer dereference (Jubin Zhong)
- Unify ECAM constants in native PCI Express drivers (Krzysztof
Wilczyński)
- Return u8 from pci_find_capability() and similar (Puranjay Mohan)
- Return u16 from pci_find_ext_capability() and similar (Bjorn
Helgaas)
- Fix ACPI companion lookup for device 0 on the root bus (Rafael J.
Wysocki)
Resource management:
- Keep both device and resource name for config space remaps
(Alexander Lobakin)
- Bounds-check command-line resource alignment requests (Bjorn
Helgaas)
- Fix overflow in command-line resource alignment requests (Colin Ian
King)
Driver binding:
- Avoid duplicate IDs in driver dynamic IDs list (Zhenzhong Duan)
Power management:
- Save/restore Precision Time Measurement Capability for
suspend/resume (David E. Box)
- Disable PTM during suspend to save power (David E. Box)
- Add sysfs attribute for device power state (Maximilian Luz)
- Rename pci_wakeup_bus() to pci_resume_bus() (Mika Westerberg)
- Do not generate wakeup event when runtime resuming device (Mika
Westerberg)
- Save/restore ASPM L1SS Capability for suspend/resume (Vidya Sagar)
Virtualization:
- Mark AMD Raven iGPU ATS as broken in some platforms (Alex Deucher)
- Add function 1 DMA alias quirk for Marvell 9215 SATA controller
(Bjorn Helgaas)
MSI:
- Disable MSI for Pericom PCIe-USB adapter (Andy Shevchenko)
- Improve warnings for 32-bit-limited MSI support (Vidya Sagar)
Error handling:
- Cache RCEC EA Capability offset in pci_init_capabilities() (Sean V
Kelley)
- Rename reset_link() to reset_subordinates() (Sean V Kelley)
- Write AER Capability only when we control it (Sean V Kelley)
- Clear AER status only when we control AER (Sean V Kelley)
- Bind RCEC devices to the Root Port driver (Qiuxu Zhuo)
- Recover from RCiEP AER errors (Qiuxu Zhuo)
- Recover from RCEC AER errors (Sean V Kelley)
- Add pcie_link_rcec() to associate RCiEPs (Sean V Kelley)
- Add pcie_walk_rcec() to RCEC AER handling (Sean V Kelley)
- Add pcie_walk_rcec() to RCEC PME handling (Sean V Kelley)
- Add RCEC AER error injection support (Qiuxu Zhuo)
Broadcom iProc PCIe controller driver:
- Fix out-of-bound array accesses (Bharat Gooty)
- Invalidate correct PAXB inbound windows (Roman Bacik)
- Enhance PCIe Link information display (Srinath Mannam)
Cadence PCIe controller driver:
- Make "cdns,max-outbound-regions" property optional (Kishon Vijay
Abraham I)
Intel VMD host bridge driver:
- Offset client MSI-X vectors (Jon Derrick)
- Update type of __iomem pointers (Krzysztof Wilczyński)
NVIDIA Tegra PCIe controller driver:
- Move "dbi" accesses to post common DWC initialization (Vidya Sagar)
- Read "dbi" base address to program in application logic (Vidya
Sagar)
- Fix ASPM-L1SS advertisement disable code (Vidya Sagar)
- Set DesignWare IP version (Vidya Sagar)
- Continue unconfig sequence even if parts fail (Vidya Sagar)
- Check return value of tegra_pcie_init_controller() (Vidya Sagar)
- Disable LTSSM during L2 entry (Vidya Sagar)
Qualcomm PCIe controller driver:
- Document PCIe bindings for SM8250 SoC (Manivannan Sadhasivam)
- Add SM8250 SoC support (Manivannan Sadhasivam)
- Add support for configuring BDF to SID mapping for SM8250
(Manivannan Sadhasivam)
Renesas R-Car PCIe controller driver:
- rcar: Drop unused members from struct rcar_pcie_host (Lad
Prabhakar)
- PCI: rcar-pci-host: Document r8a774e1 bindings (Lad Prabhakar)
- PCI: rcar-pci-host: Convert bindings to json-schema (Yoshihiro
Shimoda)
- PCI: rcar-pci-host: Document r8a77965 bindings (Yoshihiro Shimoda)
Samsung Exynos PCIe controller driver:
- Rework driver to support Exynos5433 PCIe PHY (Jaehoon Chung)
- Rework driver to support Exynos5433 variant (Jaehoon Chung)
- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)
- Add the samsung,exynos-pcie binding (Marek Szyprowski)
- Add the samsung,exynos-pcie-phy binding (Marek Szyprowski)
Synopsys DesignWare PCIe controller driver:
- Support multiple ATU memory regions (Rob Herring)
- Move intel-gw ATU offset out of driver match data (Rob Herring)
- Move "dbi", "dbi2", and "addr_space" resource setup into common
code (Rob Herring)
- Remove intel-gw unneeded function wrappers (Rob Herring)
- Ensure all outbound ATU windows are reset (Rob Herring)
- Use the common MSI irq_chip in dra7xx (Rob Herring)
- Drop the .set_num_vectors() host op (Rob Herring)
- Move MSI interrupt setup into DWC common code (Rob Herring)
- Rework MSI initialization (Rob Herring)
- Move link handling into common code (Rob Herring)
- Move dw_pcie_msi_init() into core (Rob Herring)
- Move dw_pcie_setup_rc() to DWC common code (Rob Herring)
- Remove unnecessary wrappers around dw_pcie_host_init() (Rob
Herring)
- Drop keystone duplicated 'num-viewport'" (Rob Herring)
- Move inbound and outbound windows to common struct (Rob Herring)
- Detect number of iATU windows (Rob Herring)
- Warn if non-prefetchable memory aperture size is > 32-bit (Vidya
Sagar)
- Add support to program ATU for >4GB memory (Vidya Sagar)
- Set 32-bit DMA mask for MSI target address allocation (Vidya Sagar)
TI J721E PCIe driver:
- Fix "ti,syscon-pcie-ctrl" to take argument (Kishon Vijay Abraham I)
- Add host mode dt-bindings for TI's J7200 SoC (Kishon Vijay Abraham
I)
- Add EP mode dt-bindings for TI's J7200 SoC (Kishon Vijay Abraham I)
- Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
(Kishon Vijay Abraham I)
TI Keystone PCIe controller driver:
- Enable compile-testing on !ARM (Alex Dewar)"
* tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (100 commits)
PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
PCI/ACPI: Fix companion lookup for device 0 on the root bus
PCI: Keep both device and resource name for config space remaps
PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
PCI: vmd: Update type of the __iomem pointers
PCI: iproc: Convert to use the new ECAM constants
PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
PCI: Unify ECAM constants in native PCI Express drivers
PCI: Disable PTM during suspend to save power
PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
PCI: Mark AMD Raven iGPU ATS as broken in some platforms
PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
PCI: Reduce pci_set_cacheline_size() message to debug level
PCI: Remove unused HAVE_PCI_SET_MWI
PCI: qcom: Add SM8250 SoC support
...
- Support multiple ATU memory regions (Rob Herring)
- Warn if non-prefetchable memory aperture is > 32-bit (Vidya Sagar)
- Allow programming ATU for >4GB memory (Vidya Sagar)
- Move ATU offset out of driver match data (Rob Herring)
- Move "dbi", "dbi2", and "addr_space" resource setup to common code (Rob
Herring)
- Remove unneeded function wrappers (Rob Herring)
- Ensure all outbound ATU windows are reset to reduce dependencies on
bootloader (Rob Herring)
- Use the default MSI irq_chip for dra7xx (Rob Herring)
- Drop the .set_num_vectors() host op (Rob Herring)
- Move MSI interrupt setup into DWC common code (Rob Herring)
- Rework and simplify DWC MSI initialization (Rob Herring)
- Move link handling to DWC common code (Rob Herring)
- Move dw_pcie_msi_init() calls to DWC common code (Rob Herring)
- Move dw_pcie_setup_rc() calls to DWC common code (Rob Herring)
- Remove unnecessary wrappers around dw_pcie_host_init() (Rob Herring)
- Revert "keystone: Drop duplicated 'num-viewport'" to prepare for
detecting number of iATU regions without help from DT (Rob Herring)
- Move inbound and outbound windows to common struct (Rob Herring)
- Detect number of DWC iATU windows from device registers (Rob Herring)
- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)
- Add samsung,exynos-pcie and samsung,exynos-pcie-phy bindings for
Exynos5433 variant (Marek Szyprowski)
- Rework phy-exynos-pcie driver to support Exynos5433 PCIe PHY (Jaehoon
Chung)
- Rework pci-exynos.c to support Exynos5433 PCIe host (Jaehoon Chung)
- Move tegra "dbi" accesses to post common DWC initialization (Vidya Sagar)
- Read tegra dbi" base address in application logic (Vidya Sagar)
- Fix tegra ASPM-L1SS advertisement disable code (Vidya Sagar)
- Set Tegra194 DesignWare IP version to 0x490A (Vidya Sagar)
- Continue tegra unconfig sequence even if parts fail (Vidya Sagar)
- Check return value of tegra_pcie_init_controller() (Vidya Sagar)
- Disable tegra LTSSM during L2 entry (Vidya Sagar)
- Add SM8250 SoC PCIe DT bindings and support (Manivannan Sadhasivam)
- Add SM8250 BDF to SID mapping (Manivannan Sadhasivam)
- Set 32-bit DMA mask for DWC MSI target address allocation (Vidya Sagar)
* remotes/lorenzo/pci/dwc:
PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
PCI: qcom: Add SM8250 SoC support
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
PCI: tegra: Disable LTSSM during L2 entry
PCI: tegra: Check return value of tegra_pcie_init_controller()
PCI: tegra: Continue unconfig sequence even if parts fail
PCI: tegra: Set DesignWare IP version
PCI: tegra: Fix ASPM-L1SS advertisement disable code
PCI: tegra: Read "dbi" base address to program in application logic
PCI: tegra: Move "dbi" accesses to post common DWC initialization
PCI: dwc: exynos: Rework the driver to support Exynos5433 variant
phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
PCI: dwc: Detect number of iATU windows
PCI: dwc: Move inbound and outbound windows to common struct
Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'"
PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init()
PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
PCI: dwc: Move dw_pcie_msi_init() into core
PCI: dwc: Move link handling into common code
PCI: dwc: Rework MSI initialization
PCI: dwc: Move MSI interrupt setup into DWC common code
PCI: dwc: Drop the .set_num_vectors() host op
PCI: dwc/dra7xx: Use the common MSI irq_chip
PCI: dwc: Ensure all outbound ATU windows are reset
PCI: dwc/intel-gw: Remove some unneeded function wrappers
PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
PCI: dwc/intel-gw: Move ATU offset out of driver match data
PCI: dwc: Add support to program ATU for >4GB memory
PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
PCI: dwc: Support multiple ATU memory regions
- Make "cdns,max-outbound-regions" optional (Kishon Vijay Abraham I)
- Fix "ti,syscon-pcie-ctrl" DT property to take argument (Kishon Vijay
Abraham I)
- Add TI J7200 host and endpoint mode DT bindings (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/cadence:
PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
PCI: cadence: Do not error if "cdns,max-outbound-regions" is not found
dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
- Update comment about delay before link training (Pali Rohár)
* remotes/lorenzo/pci/aardvark:
PCI: aardvark: Update comment about disabling link training
Going through a full irq descriptor lookup instead of just using the proper
helper function which provides direct access is suboptimal.
In fact it _is_ wrong because the chip callback needs to get the chip data
which is relevant for the chip while using the irq descriptor variant
returns the irq chip data of the top level chip of a hierarchy. It does not
matter in this case because the chip is the top level chip, but that
doesn't make it more correct.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201210194044.473308721@linutronix.de
Going through a full irq descriptor lookup instead of just using the proper
helper function which provides direct access is suboptimal.
In fact it _is_ wrong because the chip callback needs to get the chip data
which is relevant for the chip while using the irq descriptor variant
returns the irq chip data of the top level chip of a hierarchy. It does not
matter in this case because the chip is the top level chip, but that
doesn't make it more correct.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201210194044.364211860@linutronix.de
- Simplification and distangling of the MSI related functionality
- Let IO/APIC construct the RTE entries from an MSI message instead of
having IO/APIC specific code in the interrupt remapping drivers
- Make the retrieval of the parent interrupt domain (vector or remap
unit) less hardcoded and use the relevant irqdomain callbacks for
selection.
- Allow the handling of more than 255 CPUs without a virtualized IOMMU
when the hypervisor supports it. This has made been possible by the
above modifications and also simplifies the existing workaround in the
HyperV specific virtual IOMMU.
- Cleanup of the historical timer_works() irq flags related
inconsistencies.
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Merge tag 'x86-apic-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 apic updates from Thomas Gleixner:
"Yet another large set of x86 interrupt management updates:
- Simplification and distangling of the MSI related functionality
- Let IO/APIC construct the RTE entries from an MSI message instead
of having IO/APIC specific code in the interrupt remapping drivers
- Make the retrieval of the parent interrupt domain (vector or remap
unit) less hardcoded and use the relevant irqdomain callbacks for
selection.
- Allow the handling of more than 255 CPUs without a virtualized
IOMMU when the hypervisor supports it. This has made been possible
by the above modifications and also simplifies the existing
workaround in the HyperV specific virtual IOMMU.
- Cleanup of the historical timer_works() irq flags related
inconsistencies"
* tag 'x86-apic-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (42 commits)
x86/ioapic: Cleanup the timer_works() irqflags mess
iommu/hyper-v: Remove I/O-APIC ID check from hyperv_irq_remapping_select()
iommu/amd: Fix IOMMU interrupt generation in X2APIC mode
iommu/amd: Don't register interrupt remapping irqdomain when IR is disabled
iommu/amd: Fix union of bitfields in intcapxt support
x86/ioapic: Correct the PCI/ISA trigger type selection
x86/ioapic: Use I/O-APIC ID for finding irqdomain, not index
x86/hyperv: Enable 15-bit APIC ID if the hypervisor supports it
x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected
iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available
x86/apic: Support 15 bits of APIC ID in MSI where available
x86/ioapic: Handle Extended Destination ID field in RTE
iommu/vt-d: Simplify intel_irq_remapping_select()
x86: Kill all traces of irq_remapping_get_irq_domain()
x86/ioapic: Use irq_find_matching_fwspec() to find remapping irqdomain
x86/hpet: Use irq_find_matching_fwspec() to find remapping irqdomain
iommu/hyper-v: Implement select() method on remapping irqdomain
iommu/vt-d: Implement select() method on remapping irqdomain
iommu/amd: Implement select() method on remapping irqdomain
x86/apic: Add select() method on vector irqdomain
...
Removed unused ".bus_shift" initialisers from pci-xgene.c as
xgene_pcie_map_bus() did not use these.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-6-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Use "void __iomem" instead "char __iomem" pointer type when working with
the accessor functions (with names like readb() or writel(), etc.) to
better match a given accessor function signature where commonly the address
pointing to an I/O memory region would be a "void __iomem" pointer.
Related: https://lwn.net/Articles/102232/
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-5-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
Change interface of the function iproc_pcie_map_ep_cfg_reg() so that use
of PCI_SLOT() and PCI_FUNC() macros and most of the local ECAM-specific
constants can be dropped, and the new PCIE_ECAM_OFFSET() macro can be
used instead. Use the ALIGN_DOWN() macro to ensure that PCI Express
ECAM offset is always 32 bit aligned.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-4-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Add a custom constant for the ".bus_shift" initialiser to capture a
non-standard platform-specific ECAM bus shift value.
Standard values otherwise defined in the PCI Express Specification are
available in the include/linux/pci-ecam.h.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-3-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Add ECAM-related constants to provide a set of standard constants
defining memory address shift values to the byte-level address that can
be used to access the PCI Express Configuration Space, and then move
native PCI Express controller drivers to use the newly introduced
definitions retiring driver-specific ones.
Refactor pci_ecam_map_bus() function to use newly added constants so
that limits to the bus, device function and offset (now limited to 4K as
per the specification) are in place to prevent the defective or
malicious caller from supplying incorrect configuration offset and thus
targeting the wrong device when accessing extended configuration space.
This refactor also allows for the ".bus_shift" initialisers to be
dropped when the user is not using a custom value as a default value
will be used as per the PCI Express Specification.
Thanks to Qian Cai <qcai@redhat.com>, Michael Walle <michael@walle.cc>,
and Vladimir Oltean <olteanv@gmail.com> for reporting a pci_ecam_create()
issue with .bus_shift and to Vladimir for proposing the fix.
[bhelgaas: incorporate Vladimir's fix, update commit log]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-2-kw@linux.com
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl"
phandle. Previously a subnode to "syscon" node was added which has the
exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl
within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl"
phandle.
If the offset is not provided in "ti,syscon-pcie-ctrl", the
full memory mapped address of pcie_ctrl is used in order to maintain old
DT compatibility.
This change is as discussed in [1]
[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Link: https://lore.kernel.org/r/20201210124917.24185-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Set DMA mask to 32-bit while allocating the MSI target address so that
the address is usable for both 32-bit and 64-bit MSI capable devices.
Throw a warning if it fails to set the mask to 32-bit to alert that
devices that are only 32-bit MSI capable may not work properly.
Link: https://lore.kernel.org/r/20201117165312.25847-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
For SM8250, we need to write the BDF to SID mapping in PCIe controller
register space for proper working. This is accomplished by extracting
the BDF and SID values from "iommu-map" property in DT and writing those
in the register address calculated from the hash value of BDF. In case
of collisions, the index of the next entry will also be written.
For the sake of it, let's introduce a "config_sid" callback and do it
conditionally for SM8250.
Link: https://lore.kernel.org/r/20201208121402.178011-4-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on
SDM845. Hence the support is added reusing the members of ops_2_7_0.
The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid
callback, which will be added in successive commit.
Link: https://lore.kernel.org/r/20201208121402.178011-3-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
PCIe cards like Marvell SATA controller and some of the Samsung NVMe
drives don't support taking the link to L2 state. When the link doesn't
go to L2 state, Tegra194 requires the LTSSM to be disabled to allow PHY
to start the next link up process cleanly during suspend/resume sequence.
Failing to disable LTSSM results in the PCIe link not coming up in the
next resume cycle.
Link: https://lore.kernel.org/r/20201203133451.17716-6-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
The return value of tegra_pcie_init_controller() must be checked before
PCIe link up check and registering debugfs entries subsequently as it
doesn't make sense to do these when the controller initialization itself
has failed.
Link: https://lore.kernel.org/r/20201203133451.17716-5-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Currently the driver checks for error value of different APIs during the
uninitialization sequence. It just returns from there if there is any error
observed for one of those calls. Comparatively it is better to continue the
uninitialization sequence irrespective of whether some of them are
returning error. That way, it is more closer to complete uninitialization.
Link: https://lore.kernel.org/r/20201203133451.17716-4-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Link: https://lore.kernel.org/r/20201203133451.17716-3-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
If the absence of CLKREQ# signal is indicated by the absence of
"supports-clkreq" in the device-tree node, current driver is disabling
the advertisement of ASPM-L1 Sub-States *before* the ASPM-L1 Sub-States
offset is correctly initialized. Since default value of the ASPM-L1SS
offset is zero, this is causing the Vendor-ID wrongly programmed to 0x10d2
instead of Nvidia's 0x10de thereby the quirks applicable for Tegra194 are
not being applied. This patch fixes this issue by refactoring the
code that disables the ASPM-L1SS advertisement.
Link: https://lore.kernel.org/r/20201203133451.17716-2-vidyas@nvidia.com
Fixes: 56e15a238d ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
According to PCI Express Base Specifications (rev 4.0, 6.6.1
"Conventional reset"), after fundamental reset a 100ms delay is needed
prior to enabling link training.
Update comment in code to reflect this requirement.
Link: https://lore.kernel.org/r/20201202184659.3795-1-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
PCIe controller in Tegra194 requires the "dbi" region base address to be
programmed in one of the application logic registers to enable CPU access
to the "dbi" region. But, commit a0fd361db8 ("PCI: dwc: Move "dbi",
"dbi2", and "addr_space" resource setup into common code") moved the code
that reads the whereabouts of "dbi" region to the common code causing the
existing code in pcie-tegra194.c file to program NULL in the application
logic registers. This is causing null pointer dereference when the "dbi"
registers are accessed. This issue is fixed by explicitly reading the
"dbi" base address from DT node.
Link: https://lore.kernel.org/r/20201125192554.5401-1-vidyas@nvidia.com
Fixes: a0fd361db8 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code")
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
commit a0fd361db8 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space"
resource setup into common code") moved the code that sets up dbi_base
to DWC common code thereby creating a requirement to not access the "dbi"
region before calling common DWC initialization code. But, Tegra194
already had some code that programs some of the "dbi" registers resulting
in system crash. This patch addresses that issue by refactoring the code
to have accesses to the "dbi" region only after common DWC initialization.
Link: https://lore.kernel.org/r/20201125192234.2270-1-vidyas@nvidia.com
Fixes: a0fd361db8 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code")
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Exynos5440 SoC support has been dropped since commit 8c83315da1 ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
variant found in the Exynos5433 SoCs.
The main difference in Exynos5433 variant is lack of the MSI support
(the MSI interrupt is not even routed to the CPU).
[mszyprow: reworked the driver to support only Exynos5433 variant,
simplified code, rebased onto current kernel code, added
regulator support, converted to the regular platform driver,
removed MSI related code, rewrote commit message, added help]
Link: https://lore.kernel.org/r/20201113170139.29956-6-m.szyprowski@samsung.com
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Add logging code so that after successful linkup more comprehensive
information about PCIe link speed and link width will be displayed to
the console.
Link: https://lore.kernel.org/r/20201001060054.6616-4-srinath.mannam@broadcom.com
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Second stage bootloaders prior to Linux boot may use all inbound windows
including IARR1/IMAP1. We need to ensure that all previous configuration
of inbound windows are invalidated during the initialization stage of
the Linux iProc PCIe driver so let's add a fix to define and invalidate
IARR1/IMAP1 because it is currently missing, fixing the issue.
Link: https://lore.kernel.org/r/20201001060054.6616-3-srinath.mannam@broadcom.com
Fixes: 9415743e4c ("PCI: iproc: Invalidate PAXB address mapping")
Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Declare the full size array for all revisions of PAX register sets
to avoid potentially out of bound access of the register array
when they are being initialized in iproc_pcie_rev_init().
Link: https://lore.kernel.org/r/20201001060054.6616-2-srinath.mannam@broadcom.com
Fixes: 06324ede76 ("PCI: iproc: Improve core register population")
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Client VMD platforms have a software-triggered MSI-X vector 0 that will
not forward hardware-remapped MSI from the sub-device domain. This
causes an issue with VMD platforms that use AHCI behind VMD and have a
single MSI-X vector remapped to VMD vector 0. Add a VMD MSI-X vector
offset for these platforms.
Link: https://lore.kernel.org/r/20201102222223.92978-1-jonathan.derrick@intel.com
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
