Commit Graph

880 Commits

Author SHA1 Message Date
Ben Skeggs
dde59b9c34 drm/nouveau/imem: add some useful debug output
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
70433b904a drm/nouveau/bar/gm107-: wait for instance block binding to complete
Discovered by accident while working to use BAR2 access to instmem objects
on more paths.

We've apparently been relying on luck up until now!

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
8e644cb29c drm/nouveau/bar: initialise bar2 during oneinit
If we initialise BAR2 earlier, we're able to complete BAR1 setup using
the instmem fast-path.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
bb7e501a66 drm/nouveau/bar: prevent BAR2 mapping of objects during destructor
GP100's page table nests a lot more deeply than the GF100-compatible
layout we're currently using, which means our hackish-but-simple way
of dealing with BAR2 VMM teardown won't work anymore.

In order to sanely handle the chicken-and-egg (BAR2's PTs get mapped
into themselves) problem, we need prevent page tables getting mapped
back into BAR2 during the destruction of its VMM.

To do this, we simply key off the state that's now maintained by the
BAR2 init/fini functions.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
a78dbce9a1 drm/nouveau/bar: modify interface to bar2 vmm mapping
Match API with the BAR1 version.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
570889dc50 drm/nouveau/bar: modify interface to bar1 vmm mapping
Upcoming changes will remove the nvkm_vmm pointer from nvkm_vma, instead
requiring it to be explicitly specified on each operation.

It's not currently possible to get this information for BAR1 mappings,
so let's fix that ahead of time.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
e988952eef drm/nouveau/bar: expose interface to bar2 teardown
Will prevent spurious MMU fault interrupts if something decides to touch
BAR1 after we've unloaded the driver.

Exposed external to BAR so that INSTMEM can use it to better control the
suspend/resume fast-path access.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
48fe02478a drm/nouveau/bar: expose interface to bar2 initialisation
If we want to be able to hit the instmem fast-path in a few trickier cases,
we need to be more flexible with when we can initialise BAR2 access.

There's probably a decent case to be made for merging BAR/INSTMEM into BUS,
but that's something to ponder another day.

Flushes have been added after the write to bind the instance block,
as later commits will reveal the need for them.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
bbb163e189 drm/nouveau/bar: implement bar1 teardown
Will prevent spurious MMU fault interrupts if something decides to touch
BAR1 after we've unloaded the driver.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
7313cfa4f6 drm/nouveau/bar: move bar1 initialisation into its own function
BAR2 being done for practical reasons, this is just for consistency.

Flushes have been added after the write to bind the instance block,
as later commits will reveal the need for them.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:17 +10:00
Ben Skeggs
269fe32d33 drm/nouveau/bar: swap oneinit/init ordering, and rename bar3 to bar2
NVIDIA call it BAR2, Linux APIs treat it as BAR3 due to BAR1 being a
64-bit BAR, which I presume take two slots or something.

No actual code changes here, just to make future commits less messy.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:17 +10:00
Ben Skeggs
c9e7059296 drm/nouveau/bar: remove NV_PMC_ENABLE_PFIFO twiddling
It's handled by FIFO preinit() now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:17 +10:00
Ben Skeggs
e69dae85c9 drm/nouveau/bar/nv50,g84: drop mmu invalidate
Will already be done by MMU as a result of the PT writes that occur
during BAR2 bootstrapping.

This is likely just a left-over from the days when it was hardcoded.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:17 +10:00
Ben Skeggs
12973a37c4 drm/nouveau/secboot: add missing newline in debug message
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:17 +10:00
Jérémy Lefaure
73cef6cee7 drm/nouveau/bios/init: use ARRAY_SIZE
Using the ARRAY_SIZE macro improves the readability of the code. Also,
it is useless to re-invent it.

Found with Coccinelle with the following semantic patch:
@r depends on (org || report)@
type T;
T[] E;
position p;
@@
(
 (sizeof(E)@p /sizeof(*E))
|
 (sizeof(E)@p /sizeof(E[...]))
|
 (sizeof(E)@p /sizeof(T))
)

Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jérémy Lefaure <jeremy.lefaure@lse.epita.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:15 +10:00
Ben Skeggs
f5a5b5232b remove some useless semicolons
Reported-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:15 +10:00
Rhys Kidd
d326563738 drm/nouveau/therm/gp100: initial implementation of new gp1xx temperature sensor
v2:
 - add nv138 and drop nv13b chipsets (Ilia Mirkin)
 - refactor out status variable and instead mask tsensor (Ilia Mirkin)
 - switch SHADOWed state message away from nvkm_error() (Ilia Mirkin)
 - rename internal temperature variable (Karol Herbst)

v3:
 - use nvkm_trace() for SHADOWed state message (Ben Skeggs)

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:15 +10:00
Ben Skeggs
77913bbcb4 drm/nouveau/mmu: flush tlbs before deleting page tables
Even though we've zeroed the PDE, the GPU may have cached the PD, so we
need to flush when deleting them.

Noticed while working on replacement MMU code, but a backport might be a
good idea, so let's fix it in the current code too.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-10-03 16:34:10 +10:00
Christoph Hellwig
6faadbbb7f dmi: Mark all struct dmi_system_id instances const
... and __initconst if applicable.

Based on similar work for an older kernel in the Grsecurity patch.

[JD: fix toshiba-wmi build]
[JD: add htcpen]
[JD: move __initconst where checkscript wants it]

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jean Delvare <jdelvare@suse.de>
2017-09-14 11:59:30 +02:00
Ilia Mirkin
bc60c90f47 drm/nouveau/pci/msi: disable MSI on big-endian platforms by default
It appears that MSI does not work on either G5 PPC nor on a E5500-based
platform, where other hardware is reported to work fine with MSI.

Both tests were conducted with NV4x hardware, so perhaps other (or even
this) hardware can be made to work. It's still possible to force-enable
with config=NvMSI=1 on load.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: stable@vger.kernel.org
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:36 +10:00
Ben Skeggs
7a1af0f8bb drm/nouveau/fb/gf100-: zero mmu debug buffers
These are used for accesses to sparse mappings, and we want reads of
such mappings to return 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:33 +10:00
Ben Skeggs
485c2c91d4 drm/nouveau/bar/gf100: add config option to limit BAR2 to 16MiB
Useful for testing, and for the userspace build where we can't kick
a framebuffer driver off the device.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:33 +10:00
Ben Skeggs
6b1277c837 drm/nouveau/pmu/gt215-: abstract detection of whether reset is needed
GT215, GF100-GP100, and GP10x are all different.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:31 +10:00
Ben Skeggs
715e7d261d drm/nouveau/pmu/gt215: fix reset
The NV_PMC_ENABLE bit for PMU did not appear until GF100, and some other
unknown register needs to be poked instead.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:30 +10:00
Ben Skeggs
1ccd7d52b1 drm/nouveau/mc/gf100: add pmu to reset mask
An upcoming commit will replace direct NV_PMC register bashing from PMU
with a call to the proper function.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:30 +10:00
Karol Herbst
9d60b9c9d0 drm/nouveau/therm/gm200: Added
This allows temperature readouts on maxwell2 GPUs.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:22 +10:00
Colin Ian King
4a84a6fd9a drm/nouveau/therm: fix spelling mistake on array thresolds
Array thresolds should be named thresholds, rename it. Also make it static
static const char * const

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:22 +10:00
Ben Skeggs
38bcb208f6 drm/nouveau/bar/gf100: fix access to upper half of BAR2
Bit 30 being set causes the upper half of BAR2 to stay in physical mode,
mapped over the end of VRAM, even when the rest of the BAR has been set
to virtual mode.

We inherited our initial value from RM, but I'm not aware of any reason
we need to keep it that way.

This fixes severe GPU hang/lockup issues revealed by Wayland on F26.

Shout-out to NVIDIA for the quick response with the potential cause!

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org # 4.3+
2017-07-25 15:30:27 +10:00
Ben Skeggs
13a8651920 drm/nouveau/i2c/gf119-: add support for address-only transactions
Since switching the I2C-over-AUX helpers, there have been regressions on
some display combinations due to us not having support for "address only"
transactions.

This commits enables support for them for GF119 and newer.

Earlier GPUs have been reverted to a custom I2C-over-AUX algorithm.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-07-24 12:15:24 +10:00
Linus Torvalds
af3c8d9850 main drm pull for v4.13
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Merge tag 'drm-for-v4.13' of git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie:
 "This is the main pull request for the drm, I think I've got one later
  driver pull for mediatek SoC driver, I'm undecided on if it needs to
  go to you yet.

  Otherwise summary below:

  Core drm:
   - Atomic add driver private objects
   - Deprecate preclose hook in modern drivers
   - MST bandwidth tracking
   - Use kvmalloc in more places
   - Add mode_valid hook for crtc/encoder/bridge
   - Reduce sync_file construction time
   - Documentation updates
   - New DRM synchronisation object support

  New drivers:
   - pl111 - pl111 CLCD display controller

  Panel:
   - Innolux P079ZCA panel driver
   - Add NL12880B20-05, NL192108AC18-02D, P320HVN03 panels
   - panel-samsung-s6e3ha2: Add s6e3hf2 panel support

  i915:
   - SKL+ watermark fixes
   - G4x/G33 reset improvements
   - DP AUX backlight improvements
   - Buffer based GuC/host communication
   - New getparam for (sub)slice infomation
   - Cannonlake and Coffeelake initial patches
   - Execbuf optimisations

  radeon/amdgpu:
   - Lots of Vega10 bug fixes
   - Preliminary raven support
   - KIQ support for compute rings
   - MEC queue management rework
   - DCE6 Audio support
   - SR-IOV improvements
   - Better radeon/amdgpu selection support

  nouveau:
   - HDMI stereoscopic support
   - Display code rework for >= GM20x GPUs

  msm:
   - GEM rework for fine-grained locking
   - Per-process pagetable work
   - HDMI fixes for Snapdragon 820.

  vc4:
   - Remove 256MB CMA limit from vc4
   - Add out-fence support
   - Add support for cygnus
   - Get/set tiling ioctls support
   - Add T-format tiling support for scanout

  zte:
   - add VGA support.

  etnaviv:
   - Thermal throttle support for newer GPUs
   - Restore userspace buffer cache performance
   - dma-buf sync fix

  stm:
   - add stm32f429 display support

  exynos:
   - Rework vblank handling
   - Fixup sw-trigger code

  sun4i:
   - V3s display engine support
   - HDMI support for older SoCs
   - Preliminary work on dual-pipeline SoCs.

  rcar-du:
   - VSP work

  imx-drm:
   - Remove counter load enable from PRE
   - Double read/write reduction flag support

  tegra:
   - Documentation for the host1x and drm driver.
   - Lots of staging ioctl fixes due to grate project work.

  omapdrm:
   - dma-buf fence support
   - TILER rotation fixes"

* tag 'drm-for-v4.13' of git://people.freedesktop.org/~airlied/linux: (1270 commits)
  drm: Remove unused drm_file parameter to drm_syncobj_replace_fence()
  drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.
  amdgpu: Set cik/si_support to 1 by default if radeon isn't built
  drm/amdgpu/gfx9: fix driver reload with KIQ
  drm/amdgpu/gfx8: fix driver reload with KIQ
  drm/amdgpu: Don't call amd_powerplay_destroy() if we don't have powerplay
  drm/ttm: Fix use-after-free in ttm_bo_clean_mm
  drm/amd/amdgpu: move get memory type function from early init to sw init
  drm/amdgpu/cgs: always set reference clock in mode_info
  drm/amdgpu: fix vblank_time when displays are off
  drm/amd/powerplay: power value format change for Vega10
  drm/amdgpu/gfx9: support the amdgpu.disable_cu option
  drm/amd/powerplay: change PPSMC_MSG_GetCurrPkgPwr for Vega10
  drm/amdgpu: Make amdgpu_cs_parser_init static (v2)
  drm/amdgpu/cs: fix a typo in a comment
  drm/amdgpu: Fix the exported always on CU bitmap
  drm/amdgpu/gfx9: gfx_v9_0_enable_gfx_static_mg_power_gating() can be static
  drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup
  drm/amd/powerplay/cz: print message if smc message fails
  drm/amdgpu: fix typo in amdgpu_debugfs_test_ib_init
  ...
2017-07-09 18:48:37 -07:00
Linus Torvalds
81e3e04489 UUID/GUID updates:
- introduce the new uuid_t/guid_t types that are going to replace
    the somewhat confusing uuid_be/uuid_le types and make the terminology
    fit the various specs, as well as the userspace libuuid library.
    (me, based on a previous version from Amir)
  - consolidated generic uuid/guid helper functions lifted from XFS
    and libnvdimm (Amir and me)
  - conversions to the new types and helpers (Amir, Andy and me)
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Merge tag 'uuid-for-4.13' of git://git.infradead.org/users/hch/uuid

Pull uuid subsystem from Christoph Hellwig:
 "This is the new uuid subsystem, in which Amir, Andy and I have started
  consolidating our uuid/guid helpers and improving the types used for
  them. Note that various other subsystems have pulled in this tree, so
  I'd like it to go in early.

  UUID/GUID summary:

   - introduce the new uuid_t/guid_t types that are going to replace the
     somewhat confusing uuid_be/uuid_le types and make the terminology
     fit the various specs, as well as the userspace libuuid library.
     (me, based on a previous version from Amir)

   - consolidated generic uuid/guid helper functions lifted from XFS and
     libnvdimm (Amir and me)

   - conversions to the new types and helpers (Amir, Andy and me)"

* tag 'uuid-for-4.13' of git://git.infradead.org/users/hch/uuid: (34 commits)
  ACPI: hns_dsaf_acpi_dsm_guid can be static
  mmc: sdhci-pci: make guid intel_dsm_guid static
  uuid: Take const on input of uuid_is_null() and guid_is_null()
  thermal: int340x_thermal: fix compile after the UUID API switch
  thermal: int340x_thermal: Switch to use new generic UUID API
  acpi: always include uuid.h
  ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()
  ACPI / extlog: Switch to use new generic UUID API
  ACPI / bus: Switch to use new generic UUID API
  ACPI / APEI: Switch to use new generic UUID API
  acpi, nfit: Switch to use new generic UUID API
  MAINTAINERS: add uuid entry
  tmpfs: generate random sb->s_uuid
  scsi_debug: switch to uuid_t
  nvme: switch to uuid_t
  sysctl: switch to use uuid_t
  partitions/ldm: switch to use uuid_t
  overlayfs: use uuid_t instead of uuid_be
  fs: switch ->s_uuid to uuid_t
  ima/policy: switch to use uuid_t
  ...
2017-07-03 09:55:26 -07:00
Ben Skeggs
0d93cd92bd drm/nouveau/disp/nv50-: implement a common supervisor 3.0
This makes use of all the additional routing and state added in previous
commits, making it possible to deal with GM20x macro link routing, while
also sharing code between the NV50 and GF119 implementations.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:05:00 +10:00
Ben Skeggs
4fdc6ba32e drm/nouveau/fb/ram/nv40-: use new devinit script interpreter entry-point
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:45 +10:00
Ben Skeggs
28c62976a8 drm/nouveau/devinit: use new devinit script interpreter entry-point
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:44 +10:00
Ben Skeggs
b88afa4396 drm/nouveau/bios/init: add or/link args separate from output path
As of DCB 4.1, these are not the same thing.

Compatibility temporarily in place until callers have been updated.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:44 +10:00
Ben Skeggs
ca9c2d5b28 drm/nouveau/bios/init: bump script offset to 32-bits
No (known) case yet, but other tables have been moving beyond 16-bits,
so we may as well be prepared.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:43 +10:00
Ben Skeggs
2195a22f6d drm/nouveau/bios/init: rename 'crtc' to 'head'
Compatibility temporarily in place until all callers have been updated.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:43 +10:00
Ben Skeggs
5b0e787ad5 drm/nouveau/bios/init: remove internal use of nvbios_init.bios
We already have a subdev pointer, from which we can locate the device's
BIOS subdev.  No need for a separate pointer.

Structure/callers not updated yet, as I want to batch more changes and
only touch the callers once.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:42 +10:00
Ben Skeggs
4bb4a7466a drm/nouveau/bios/init: rename nvbios_init() to nvbios_devinit()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:42 +10:00
Ben Skeggs
7eaf1198a9 drm/nouveau/tmr: remove nvkm_timer_alarm_cancel()
nvkm_timer_alarm() already handles this as part of protecting against
callers passing in no timeout value.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:42 +10:00
Karol Herbst
4dc33b1222 drm/nouveau/bios/iccsense: rails for power sensors have a mask of 0xf8 for version 0x10
I only saw those values inside the vbios: 0xff, 0xfd, 0xfc, 0xfa for valid
rails.

No idea what the lower value does, but at least we get power readings on
a lot of Fermi GPUs with that.

v2: add missing parentheses

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:19 +10:00
Karol Herbst
c0cd04700f drm/nouveau/bios/volt: Parse min and max for Version 0x40
This is according to what we have in nvbios.

Fixes "ERROR: Can't get value of subfeature in0_min: Can't read" errors
in sensors for some GPUs.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16 14:04:19 +10:00
Andy Shevchenko
94116f8126 ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()
acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16
bytes. Instead we convert them to use guid_t type. At the same time we
convert current users.

acpi_str_to_uuid() becomes useless after the conversion and it's safe to
get rid of it.

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Cc: Amir Goldstein <amir73il@gmail.com>
Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Cc: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Acked-by: Joerg Roedel <jroedel@suse.de>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-06-07 12:20:49 +02:00
Ben Skeggs
b4e382ca75 drm/nouveau/tmr: fully separate alarm execution/pending lists
Reusing the list_head for both is a bad idea.  Callback execution is done
with the lock dropped so that alarms can be rescheduled from the callback,
which means that with some unfortunate timing, lists can get corrupted.

The execution list should not require its own locking, the single function
that uses it can only be called from a single context.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-06-06 14:04:07 +10:00
Christophe JAILLET
563ad2b640 drm/nouveau/secboot: plug memory leak in ls_ucode_img_load_gr() error path
The last goto looks spurious because it releases less resources than the
previous one.
Also free 'img->sig' if 'ls_ucode_img_build()' fails.

Fixes: 9d896f3e41 ("drm/nouveau/secboot: abstract LS firmware loading functions")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-05-17 09:09:41 +10:00
Ben Skeggs
e4311ee51d drm/nouveau/therm: remove ineffective workarounds for alarm bugs
These were ineffective due to touching the list without the alarm lock,
but should no longer be required.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-05-12 08:32:58 +10:00
Ben Skeggs
330bdf62fe drm/nouveau/tmr: avoid processing completed alarms when adding a new one
The idea here was to avoid having to "manually" program the HW if there's
a new earliest alarm.  This was lazy and bad, as it leads to loads of fun
races between inter-related callers (ie. therm).

Turns out, it's not so difficult after all.  Go figure ;)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-05-12 08:32:58 +10:00
Ben Skeggs
9fc64667ee drm/nouveau/tmr: fix corruption of the pending list when rescheduling an alarm
At least therm/fantog "attempts" to work around this issue, which could
lead to corruption of the pending alarm list.

Fix it properly by not updating the timestamp without the lock held, or
trying to add an already pending alarm to the pending alarm list....

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-05-12 08:32:57 +10:00
Ben Skeggs
1b0f84380b drm/nouveau/tmr: handle races with hw when updating the next alarm time
If the time to the next alarm is short enough, we could race with HW and
end up with an ~4 second delay until it triggers.

Fix this by checking again after we update HW.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-05-12 08:32:57 +10:00
Ben Skeggs
3733bd8b40 drm/nouveau/tmr: ack interrupt before processing alarms
Fixes a race where we can miss an alarm that triggers while we're already
processing previous alarms.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-05-12 08:32:57 +10:00
Ben Skeggs
80a92865f2 drm/nouveau/fb/ram/gf100-: remove 0x10f200 read
This reg has moved on Pascal, and causes a bus fault.

We never use the value anyway, so just remove the read.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-05-12 08:32:53 +10:00
Mario Kleiner
271393ba6e drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection
A missing u64 cast causes a 32-Bit wraparound from
4096 MiB to 0 MiB and therefore total 0 MiB VRAM detected
if card has 4096 Mib per FBP.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-29 22:39:23 +10:00
Wei Yongjun
48907c23ea drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr()
The error return code PTR_ERR(mc) is always 0 since mc is
equal to 0 in this error handling case.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-29 22:39:23 +10:00
Ben Skeggs
a7cb78bab3 drm/nouveau/bios/bitP: check that table is long enough for optional pointers
Fixes OOB VBIOS accesses on some boards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-29 22:39:23 +10:00
Adam Borowski
99a97a8ba9 drm/nouveau/gpio: enable interrupts on cards with 32 gpio lines
The code attempts to enable them, but hits an undefined behaviour by
shifting by the entire register's width:

    int lines = 32;
    u32 mask = (1 << lines) - 1;    // 00000000 on x86
    u32 mask = (1 << lines) - 1;    // ffffffff on arm (32)
    u32 mask = (1 << lines) - 1;    // 00000000 on arm64
    u32 mask = (1ULL << lines) - 1; // ffffffff everywhere

Signed-off-by: Adam Borowski <kilobyte@angband.pl>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:53:50 +10:00
Alexandre Courbot
0af0327cd9 drm/nouveau/ibus: add GP10B support
GP10B requires a specific initialization sequence due to the absence of
devinit.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
b9a995def6 drm/nouveau/mc: add GP10B support
GP10B's MC is compatible with GP100's, but engines need to be explicitly
put out of ELPG during init.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
fdde00ed11 drm/nouveau/fb: add GP10B support
GP10B's FB is largely compatible with the GP100 implementation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
59d5592d3b drm/nouveau/secboot: add GP10B support
GP10B's secboot is largely similar to GM20B's. Only differences are MC
base address and the fact that GPCCS is also securely managed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
c79505c1f9 drm/nouveau/secboot/gm20b: specify MC base address as argument
Allow the MC base address to be specified as an argument for the WPR
region reading function. GP10B uses a different address layout as GM20B,
so this is necessary. Also export the function to be used by GP10B.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
008796d9a3 drm/nouveau/secboot: start LS firmware in post-run hook
The LS firmware post-run hook is the right place to start said LS
firmware. Moving it here also allows to remove special handling in the
ACR code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
d424d278b2 drm/nouveau/secboot: let LS post_run hooks return error
A LS post-run hook can meet an error meaning the failure of secure boot.
Make sure this can be reported.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
2963a06a4d drm/nouveau/secboot: pass instance to LS firmware loaders
Having access to the secboot instance loading a LS firmware can be
useful to LS firmware handlers. At least more useful than just having an
out-of-context subdev pointer.

GP10B's firmware will also need to know the WPR address, which can be
obtained from the secboot instance.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00
Alexandre Courbot
598a8148e7 drm/nouveau/secboot: allow to boot multiple falcons
Change the secboot and msgqueue interfaces to take a mask of falcons to
reset instead of a single falcon. The GP10B firmware interface requires
FECS and GPCCS to be booted in a single firmware command.

For firmwares that only support single falcon boot, it is trivial to
loop over the mask and boot each falcons individually.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:03 +10:00
Thierry Reding
e5ffa727e5 drm/nouveau/imem/gk20a: Turn instmem lock into mutex
The gk20a implementation of instance memory uses vmap()/vunmap() to map
memory regions into the kernel's virtual address space. These functions
may sleep, so protecting them by a spin lock is not safe. This triggers
a warning if the DEBUG_ATOMIC_SLEEP Kconfig option is enabled. Fix this
by using a mutex instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:03 +10:00
Alexandre Courbot
b7d6c8db49 drm/nouveau/secboot: fix NULL pointer dereference
The msgqueue pointer validity should be checked by its owner, not by the
msgqueue code itself to avoid this situation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-17 12:06:58 +10:00
Alexandre Courbot
aa7fc0ca75 drm/nouveau/secboot: fix inconsistent pointer checking
We were returning PTR_ERR() on a NULL pointer, which obviously won't
work. nvkm_engine_ref() will return an error in case something went
wrong.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-17 10:08:24 +10:00
Ben Skeggs
97e5268d57 drm/nouveau/fb/gf100-: rework ram detection
This commit reworks the RAM detection algorithm, using RAM-per-LTC to
determine whether a board has a mixed-memory configuration instead of
using RAM-per-FBPA.  I'm not certain the algorithm is perfect, but it
should handle all currently known configurations in the very least.

This should fix GTX 970 boards with 4GiB of RAM where the last 512MiB
isn't fully accessible, as well as only detecting half the VRAM on
GF108 boards.

As a nice side-effect, GP10x memory detection now reuses the majority
of the code from earlier chipsets.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:17 +10:00
Ben Skeggs
ba4c063d47 drm/nouveau/fb/gm200: split ram implementation from gm107
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:17 +10:00
Ben Skeggs
904e703c80 drm/nouveau/fb/gf108: split implementation from gf100
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:17 +10:00
Ben Skeggs
fcb371a1d5 drm/nouveau/fb/gf100-: modify constructors to allow more customisation
GF108/GM107 implementations will want slightly different functions for
the upcoming RAM detection improvements.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:17 +10:00
Ben Skeggs
5c68d91ee0 drm/nouveau/i2c/g94-: return REPLY_M value on reads
This value represents the actual number of bytes recieved on the AUX
channel as the result of a read transaction.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:16 +10:00
Ben Skeggs
1af5c410cc drm/nouveau/i2c: modify aux interface to return length actually transferred
Apparently sinks are allows to respond with ACK even if they didn't
fully complete a transaction...  It seems like a missed opportunity
for DEFER to me, but what do I know :)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:16 +10:00
Alexandre Courbot
5429f82f34 drm/nouveau/secboot: add gp102/gp104/gp106/gp107 support
These gp10x chips are supporting using (roughly) the same firmware.
Compared to previous secure chips, ACR runs on SEC2 and so does the
low-secure msgqueue.

ACR for these chips is based on r367.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:16 +10:00
Alexandre Courbot
84074e5b10 drm/nouveau/secboot: put HS code loading code into own file
We will also need to load HS blobs outside of acr_r352 (for instance, to
run the NVDEC VPR scrubber), so make this code reusable.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:16 +10:00
Alexandre Courbot
717bad8273 drm/nouveau/secboot: support for r375 ACR
r375 ACR uses a unified bootloader descriptor for the GR and PMU
firmwares.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:16 +10:00
Alexandre Courbot
0f8fb2ab1e drm/nouveau/secboot: support for r367 ACR
r367 uses a different hsflcn_desc layout and LS firmware signature
format, requiring a rewrite of some functions.

It also makes use of the shadow region, and uses SEC as the boot falcon.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:16 +10:00
Alexandre Courbot
810997ff40 drm/nouveau/secboot: support for r364 ACR
r364 is similar to r361, but uses a different hsflcn_desc structure to
introduce the shadow region address (even though it is not yet used by
this version).

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:15 +10:00
Alexandre Courbot
ec91cb0285 drm/nouveau/secboot: workaround bug when starting SEC2 firmware
For some unknown reason the LS SEC2 firmware needs to be started twice
to operate. Detect and address that condition.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:15 +10:00
Alexandre Courbot
c5e1fef487 drm/nouveau/secboot: support standard NVIDIA HS binaries
I had the brilliant idea to "improve" the binary format by removing
a useless indirection in the HS binary files. In the end it just
makes things more complicated than they ought to be as NVIDIA-provided
files need to be adapted. Since the format used can be identified by the
header, support both.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:15 +10:00
Alexandre Courbot
b58b417163 drm/nouveau/secboot: support for unload blob bootloader
If the load and unload falcons are different, then a different
bootloader must also be used. Support this case.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:14 +10:00
Alexandre Courbot
c93cfe35c4 drm/nouveau/secboot: let callers interpret return value of blobs
Since the HS blobs are provided and signed by NVIDIA, we cannot expect
always-consistent behavior. In this case, on GP10x the unload blob may
return 0x1d even though things have run perfectly well. This behavior
has been confirmed by NVIDIA.

So let the callers of the run_blob() hook receive the blob return's
value (a positive integer) and decide what it means. This allows us to
workaround the 0x1d code instead of issuing an error.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
7defd1daac drm/nouveau/secboot: support for different load and unload falcons
On some secure boot instances (e.g. gp10x) the load and unload blobs do
not run on the same falcon. Support this case by introducing a new
member to the ACR structure and making related functions take the falcon
to use as an argument instead of assuming the boot falcon is to be used.

The rule is that the load blob can be run on either the SEC or PMU
falcons, but the unload blob must be always run on PMU.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
a13edd0b21 drm/nouveau/secboot: share r361 BL structures and functions
Share elements of r361 that will be reused in other ACRs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
114223aa1a drm/nouveau/secboot: add support for SEC LS firmware
Support running a message queue firmware on SEC.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
48387f0ca5 drm/nouveau/secboot: support running ACR on SEC
Add support for running the ACR binary on the SEC falcon.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
c3433603ca drm/nouveau/secboot: get start address of blob from ACR
The start address used for secure blobs is not unique to the ACR, but
rather blob-dependent. Remove the unique member stored in the ACR
structure and make the load function return the start address for the
current blob instead.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
e9462417f1 drm/nouveau/secboot: add shadow blob argument
ACR firmware from r364 on need a shadow region for the ACR to copy the
WPR region into. Add a flag to indicate that a shadow region is required
and manage memory allocations accordingly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
b62880f796 drm/nouveau/core: add SEC2 engine
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
Alexandre Courbot
9e4397579f drm/nouveau/falcon: delay construction of falcons to oneinit()
Reading registers at device construction time can be harmful, as there
is no guarantee the underlying engine will be up, or in its runtime
configuration. Defer register reading to the oneinit() hook and update
users accordingly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
1106459e9f drm/nouveau/secboot/gm20b: enable PMU firmware
Enable the PMU firmware in gm20b, managed by secure boot.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
937deb06d0 drm/nouveau/pmu/gm20b: add msgqueue support
gm20b PMU firmware is driven by a msgqueue, so connect relevant PMU
hooks to their msgqueue counterparts.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
fc12745717 drm/nouveau/secboot: check that WPR region is properly set
The ACR firmware may return no error but fail nonetheless. Such cases
can be detected by verifying that the WPR region has been properly set
in FB. If this is not the case, this is an error, but the unload
firmware should still not be run.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
7775d0dcb2 drm/nouveau/secboot: support optional falcons
PMU support has been enabled for r352 ACR, but it must remain optional
if we want to preserve existing user-space that do not include it. Allow
ACR to be instanciated with a list of optional LS falcons, that will not
produce a fatal error if their firmware is not loaded. Also change the
secure boot bootstrap logic to be able to fall back to legacy behavior
if it turns out the boot falcon's LS firmware cannot be loaded.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
bb5ec9c9dd drm/nouveau/secboot: support PMU LS firmware
Add the PMU bootloader generator and PMU LS ops that will enable proper
PMU operation if the PMU falcon is designated as managed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
7579e22f38 drm/nouveau/secboot: base support for PMU falcon
Adapt secboot's behavior if a PMU firmware is present, in particular
the way LS falcons are reset. Without PMU firmware, secboot needs to be
performed again from scratch so all LS falcons are reset. With PMU
firmware, we can ask the PMU's ACR unit to reset a specific falcon
through a PMU message.

As we must preserve the old behavior to avoid breaking user-space, add a
few conditionals to the way falcons are reset.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
eabe4ea6a4 drm/nouveau/secboot: support for loading LS PMU firmware
Allow secboot to load a LS PMU firmware. LS PMU is one instance of
firmwares based on the message queue mechanism, which is also used for
other firmwares like SEC, so name its source file accordingly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
9ce480fead drm/nouveau/pmu: add msgqueue member
NVIDIA-provided PMU firmware is controlled by a msgqueue. Add a member
to the PMU structure as well as the required cleanup code if this
feature is used.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
0117b3369f drm/nouveau/secboot: add LS firmware post-run hooks
Add the ability for LS firmwares to declare a post-run hook that is
invoked right after the HS firmware is executed. This allows them to
e.g. write some initialization data into the falcon's DMEM.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
9bb55bb79f drm/nouveau/secboot: abstract fixup_hs_desc function
As different firmare versions use different HS descriptor formats, we
need to abstract this part as well.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
f7152a232c drm/nouveau/secboot: make specialized ls_ucode_img struct private
This structure does not need to be shared anymore.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
48eee549da drm/nouveau/secboot: store ucode offset in base image structure
This allows the bootloader descriptor generation code to not rely on
specialized ls_ucode_img structures, making it reusable in other
instances.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:12 +10:00
Alexandre Courbot
5c4e0602d6 drm/nouveau/secboot: fix usage of hsf_load_header
Offsets were not properly computed. This went unnoticed because we are
only using one app for now.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
913b97f944 drm/nouveau/secboot: prevent address trimming
Using 32-bit integers would trim the WPR address if it is allocated above 4GB.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
098ee77224 drm/nouveau/secboot: fix WPR region alignment
A WPR region smaller than 256K will result in secure boot failure.
Adjust the minimal size.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
3e8fbe3191 drm/nouveau/secboot: fix WPR address to be 64-bit
The WPR address parameter of the ls_write_wpr hook was defined as a u32,
which will very likely overflow on boards with more than 4GB VRAM.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
a335f078df drm/nouveau/secboot: make sure requested falcons are supported
Check at contruction time that we have support for all the LS firmwares
asked by the caller.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
489a5fe868 drm/nouveau/secboot: remove unused hook
Remove a leftover that became obsolete with the falcon interface.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
485a20eff2 drm/nouveau/pmu: make sure the reset hook exists before running it
Some PMU implementations (in particular the ones managed by secure
boot) may not have a reset() hook. Make sure we don't crash in that
case.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Alexandre Courbot
ba735d061d drm/nouveau/secboot: make nvkm_secboot_falcon_name visible
Make nvkm_secboot_falcon_name publicly visible as other subdevs will
need to use it for debug messages.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Ben Skeggs
69d468f477 drm/nouveau/priv: punt messages to debug level
Ideally we'd be able to keep these at a more obvious error level, as
they're a good indication of us doing something wrong.

However, NVIDIA's FECS/GPCCS firmware touches registers that trigger
priv ring faults, and we can't do anything to fix that ourselves due
to the need for them to be signed by NVIDIA.

This issue was reported a while back, but hasn't been fixed, so, for
now we will hide the messages to prevent spamming Optimus users with
messages whenever the NVIDIA GPU is powered off and on again.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:11 +10:00
Karol Herbst
5112abc6a4 drm/nouveau/pci/g92: Fix rearm
704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs.

g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm.

Reported-by: Andrew Randrianasulu <randrianasulu@gmail.com>
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2017-02-17 17:38:18 +10:00
Martin Peres
800efb4c28 drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios
This seems to be absolutely necessary for a lot of NV40.

Reported-by: gsgf on IRC/freenode
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:17 +10:00
Karol Herbst
1efc3c4b9f drm/nouveau/iccsense: Parse max and crit power level
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:16 +10:00
Karol Herbst
e5f8eabc00 drm/nouveau/bios/power_budget: Add basic power budget parsing
v2: Set entry to 0xff if not found
    Add cap entry for ver 0x30 tables
    Rework to fix memory leak
v3: More error checks
    Simplify check for invalid entries
v4: disable for ver 0x10 for now
    move assignments after the second last return

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:16 +10:00
Ben Skeggs
13416077e5 drm/nouveau/top: add function to translate subdev index to mmu fault id
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:11 +10:00
Karol Herbst
725af74826 drm/nouveau/pci: Rename g94 to g92
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:06 +10:00
Ben Skeggs
9f1c4dbd3d drm/nouveau/devinit/nv50: return error code if pll calculation fails
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:05 +10:00
Ilia Mirkin
0879683280 drm/nouveau: fix bug id typo in comment
The issue was recorded in fd.o bug 27501, not 25701.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:05 +10:00
Ben Skeggs
d2ee360564 drm/nouveau/core/memory: distinguish between coherent/non-coherent targets
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:15:01 +10:00
Ben Skeggs
134fdc1a70 drm/nouveau/core/mm: replace region list with next pointer
We never have any need for a double-linked list here, and as there's
generally a large number of these objects, replace it with a single-
linked list in order to save some memory.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:15:01 +10:00
Ben Skeggs
af7db03e1b replace BUG_ON(1) with BUG()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:55 +10:00
Ben Skeggs
7eb7497e55 drm/nouveau/fb/ram/gk104: remove unused best_clk variable
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
63f542e473 drm/nouveau/secboot: clear halt interrupt after ACR is run
The halt interrupt must be cleared after ACR is run, otherwise the LS
PMU firmware will not be able to run.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
425c816a80 drm/nouveau/secboot: add lazy-bootstrap flag
When the PMU firmware is present, the falcons it manages need to have
the lazy-bootstrap flag of their WPR header set so the ACR does not boot
them. Add support for this.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
64a94ded89 drm/nouveau/secboot: fix WPR descriptor generation
Generate the WPR descriptor closer to what RM does. In particular, set
the expected masks, and only set the ucode members on Tegra.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
45ef845009 drm/nouveau/secboot: set default error value in error register
Set a default error value in the mailbox 0 register so we can catch
cases where the secure boot binary fails early without being able to
report anything.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
b606234e2f drm/nouveau/secboot: add missing fields to BL structure
Since DMEM was initialized to zero, these fields went unnoticed. Add
them for safety.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
b2888c650e drm/nouveau/secboot: safer zeroing of BL descriptors
Perform the zeroing of BL descriptors in the caller function instead of
trusting each generator will do it. This could avoid a few pulled hairs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
9d896f3e41 drm/nouveau/secboot: abstract LS firmware loading functions
The WPR and LSB headers, used to generate the LS blob, may have a
different layout and sizes depending on the driver version they come
from. Abstract them and confine their use to driver-specific code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
9839307cfe drm/nouveau/secboot: remove ls_ucode_mgr
This was used only locally to one function and can be replaced by ad-hoc
variables.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
88490323e4 drm/nouveau/secboot: remove unneeded ls_ucode_img member
ucode_header is not used anywhere, so just get rid of it.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:32 +10:00
Alexandre Courbot
3454a034b7 drm/nouveau/secboot: disable falcon interrupts when running blob
Make sure we are not disturbed by spurious interrupts, as we poll the
halt bit anyway.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
555cafb404 drm/nouveau/secboot: split reset function
Split the reset function into more meaningful and reusable ones.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
8a50452c89 drm/nouveau/secboot: add LS flags to LS func structure
Add a flag that can be set when declaring how a LS firmware should be
loaded. This allows us to remove falcon-specific code in the loader.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
72e0642fb4 drm/nouveau/secboot: reorganize into more files
Split the act of building the ACR blob from firmware files from the rest
of the (chip-dependent) secure boot logic. ACR logic is moved into
acr_rxxx.c files, where rxxx corresponds to the compatible release of
the NVIDIA driver. At the moment r352 and r361 are supported since
firmwares have been released for these versions. Some abstractions are
added on top of r352 so r361 can easily be implemented on top of it by
just overriding a few hooks.

This split makes it possible and easy to reuse the same ACR version on
different chips. It also hopefully makes the code much more readable as
the different secure boot logics are separated. As more chips and
firmware versions will be supported, this is a necessity to not get lost
in code that is already quite complex.

This is a big commit, but it essentially moves things around (and split
the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code
semantics should not be affected.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
8f491c892e drm/nouveau/secboot: generate HS BL descriptor in hook
Use the HS hook to completely generate the HS BL descriptor, similarly
to what is done in the LS hook, instead of (arbitrarily) using the
acr_v1 format as an intermediate.

This allows us to make the bootloader descriptor structures private to
each implementation, resulting in a cleaner an more consistent design.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
e781ff9118 drm/nouveau/secboot: add low-secure firmware hooks
Secure firmwares provided by NVIDIA will follow the same overall
principle, but may slightly differ in format, or not use the same
bootloader descriptor even on the same chip. In order to handle
this as gracefully as possible, turn the LS firmware functions into
hooks that can be overloaded as needed.

The current hooks cover the external firmware loading as well as the
bootloader descriptor generation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
a9b333a50e drm/nouveau/secboot: remove fixup_hs_desc hook
This hook can be removed if the function writing the HS
descriptor is aware of WPR settings. Let's do that as it allows us to
make the ACR descriptor structure private and save some code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
808d6efdeb drm/nouveau/secboot: rename init() hook to oneinit()
The init() hook is called by the subdev's oneinit(). Rename it
accordingly to avoid confusion about the lifetime of objects allocated
in it.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
c8225b54fe drm/nouveau/secboot: remove nvkm_secboot_start()
Since GR has moved to using the falcon library to start the falcons,
this function is not needed anymore.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
d72fb36c45 drm/nouveau/secboot: use falcon library
Use the falcon library functions in secure boot. This removes a lot of
code and makes the secure boot flow easier to understand as no register
is directly accessed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
236f474791 drm/nouveau/secboot: fix functions definitions
These functions should use the nvkm_secboot_falcon enum. Fix this.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
b1c39d801a drm/nouveau/gm20b: add dummy PMU device
Add a dummy PMU device so the PMU falcon is instanciated and can be used
by secure boot.

We could reuse gk20a's implementation here, but it would fight with
secboot over PMU falcon's ownership and secboot will reset the PMU,
preventing it from operating afterwards. Proper handout between secboot
and pmu is coming along with the actual gm20b PMU implementation, so
use this as a temporary solution.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
9b071c7935 drm/nouveau/pmu/gk20a: use falcon library functions
Use the falcon library functions where relevant.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
68d82161fd drm/nouveau/pmu/gk20a: simplify code a bit
Some functions always succeed - change their return type to void and
remove the error-handling code in their caller.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:31 +10:00
Alexandre Courbot
d8711c5a9c drm/nouveau/pmu/gk20a: use nvkm_pmu_ctor()
Use the PMU constructor so that all base members (in particular the
falcon instance) are initialized properly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
1e2115d8c0 drm/nouveau/pmu: instanciate the falcon in PMU device
Have an instance of nvkm_falcon in the PMU structure, ready to be used
by other subdevs (i.e. secboot).

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
e72da6e04f drm/nouveau/pmu: add nvkm_pmu_ctor() function
Add a PMU constructor so implementations that extend the nvkm_pmu
structure can have all base members properly initialized.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Alexandre Courbot
c599dd4b70 drm/nouveau/mc: add nvkm_mc_enabled() function
Add a function that allows us to query whether a given subdev is
currently enabled or not.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:14:30 +10:00
Ben Skeggs
79d48dadb0 drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-12-13 11:40:16 +10:00
Ben Skeggs
f4e65efc88 drm/nouveau/ltc: protect clearing of comptags with mutex
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2016-12-13 11:40:09 +10:00
Ben Skeggs
a8f6cb7bb3 drm/nouveau/mxm: warn more loudly on unsupported DCB version
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-12-06 09:08:23 +10:00
Ben Skeggs
f6bf17391f drm/nouveau/mxm: handle DCB 4.1 modification
Allows MXM DCB modification to be handled on GM20x and newer boards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-12-06 09:08:23 +10:00
Ben Skeggs
8ca99316fd drm/nouveau/bios/mxm: handle digital connector table 1.1
I suspect the version bump is just to signify that the table now specifies
pad macro/links instead of SOR/sublinks.

For our usage of the table, just recognising the new version is enough.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-12-06 09:08:23 +10:00
Ben Skeggs
02099bac65 drm/nouveau/fb/ram/gp100-: fix memory detection where FBP_NUM != FBPA_NUM
In this situation, we'd have ended up detecting less VRAM than we have.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:35 +10:00
Ben Skeggs
ff5354120f drm/nouveau/bios/volt: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:35 +10:00
Ben Skeggs
60fb7064e4 drm/nouveau/bios/vmap: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:35 +10:00
Ben Skeggs
1957d3d568 drm/nouveau/bios/timing: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:35 +10:00
Ben Skeggs
a215721fb6 drm/nouveau/bios/therm: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:35 +10:00
Ben Skeggs
8f6a5ab9b1 drm/nouveau/bios/perf: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:35 +10:00
Ben Skeggs
5764ff609d drm/nouveau/bios/iccsense: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:34 +10:00
Ben Skeggs
4a8daacf50 drm/nouveau/bios/fan: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:34 +10:00
Ben Skeggs
6496b4e5ab drm/nouveau/bios/cstep: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:34 +10:00
Ben Skeggs
5878601767 drm/nouveau/bios/boost: pointers are 32-bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28 15:39:34 +10:00
Ben Skeggs
eeea423c48 drm/nouveau/fb/gp102: rename from gp104
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:39 +10:00
Ben Skeggs
dc2b655928 drm/nouveau/devinit/gm200: drop pmu reset sequence
This sequence is incorrect for GP102/GP104 boards.  This is now being
handled correctly by the PMU subdev during preinit();

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:37 +10:00
Ben Skeggs
920c58a711 drm/nouveau/devinit/gm200: replace while loops with PTIMER-based timeout loops
It appears to be safe to access PTIMER on an unposted board with newer
chipsets.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:37 +10:00
Ben Skeggs
d91ccec631 drm/nouveau/pmu/gp102: initial implementation
GP102/GP104 require a harder reset of PMU prior to DEVINIT, or the IFR
image will hang.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:37 +10:00
Ben Skeggs
41c7be6913 drm/nouveau/pmu/gp100: initial implementation
Just enough to hookup preinit reset(), which DEVINIT will depend on later.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:36 +10:00
Ben Skeggs
2f524aa0b7 drm/nouveau/pmu: execute reset before running devinit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:36 +10:00
Ben Skeggs
da7d2062fc drm/nouveau/pmu: move ucode handling into gt215 implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-17 09:50:36 +10:00
Ben Skeggs
f3a8b6645d drm/nouveau: silence sparse warnings about symbols not being marked static
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:40 +10:00
Alexandre Courbot
770b06e8cb drm/nouveau/fb: add gm20b device
gm20b's FB has the same capabilities as gm200, minus the ability to
allocate RAM. Create a device that reflects this instead of re-using the
gk20a device which may be incorrect.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-By: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:39 +10:00
Alexandre Courbot
60958b8f29 drm/nouveau/fb/gk20a: use regular gf100's functions
gk20a's FB is not special compared to other Kepler chips, besides the
fact it does not have VRAM. Use the regular gf100 hooks instead of the
incomplete versions we rewrote.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-By: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:39 +10:00
Alexandre Courbot
635cb7da57 drm/nouveau/fb/gk20a: fix constructor call
The gf100 constructor should be called, otherwise we will allocate a
smaller object than expected. This was without effect so far because
gk20a did not allocate a page, but with gf100's page allocation moved
to the oneinit() hook this problem has become apparent.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:38 +10:00
Alexandre Courbot
ed7acfae2a drm/nouveau/pmu: remove reset() hook
The reset hook of pmu_func is never called, and gt215 was the only chip
to implement. Remove this dead code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:38 +10:00
Baoyou Xie
e08a1d97d3 drm/nouveau: mark symbols static where possible
We get a few warnings when building kernel with W=1:
drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c:29:1: warning: no previous prototype for 'nvbios_fan_table' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c:56:1: warning: no previous prototype for 'nvbios_fan_entry' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c:184:1: warning: no previous prototype for 'gt215_clk_info' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c:99:1: warning: no previous prototype for 'gt215_link_train_calc' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c:153:1: warning: no previous prototype for 'gt215_link_train' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c:271:1: warning: no previous prototype for 'gt215_link_train_init' [-Wmissing-prototypes]
....

In fact, both functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:36 +10:00
Baoyou Xie
e8390eb260 drm/nouveau: add missing header dependencies
We get a few warnings when building kernel with W=1:
drivers/gpu/drm/nouveau/nvkm/core/firmware.c:34:1: warning: no previous prototype for 'nvkm_firmware_get' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/core/firmware.c:58:1: warning: no previous prototype for 'nvkm_firmware_put' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c:69:1: warning: no previous prototype for 'nvkm_sddr3_calc' [-Wmissing-prototypes]
drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c:60:1: warning: no previous prototype for 'nvkm_sddr2_calc' [-Wmissing-prototypes]
....

In fact, these functions are declared in
drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
drivers/gpu/drm/nouveau/dispnv04/disp.h.
So this patch adds missing header dependencies.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:35 +10:00
Ben Skeggs
f1963a47c0 drm/nouveau/i2c/aux/g94-: retry transactions after hw reports an error
This fixes (works around?) link training failures seen on (at least)
the Lenovo P50's internal panel.

It's also an important fix on the same system for MST support on the
dock.  Sometimes, right after receiving an IRQ from the sink, there's
an error bit (SINKSTAT_ERR) set in the DPAUX registers before we've
even attempted a transaction.

v2. Fixed regression on passive DP->DVI adapters.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:30 +10:00
Ben Skeggs
4d98773081 drm/nouveau/mxm: add some extra debug output
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-07 14:04:13 +10:00
Ben Skeggs
5dc7f4aa9d drm/nouveau/bios: require checksum to match for fast acpi shadow method
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2016-11-07 14:03:36 +10:00
Ard Biesheuvel
2ecf7c43d7 drm/nouveau/fb/nv50: defer DMA mapping of scratch page to oneinit() hook
The 100c08 scratch page is mapped using dma_map_page() before the TTM
layer has had a chance to set the DMA mask. This means we are still
running with the default of 32 when this code executes, and this causes
problems for platforms with no memory below 4 GB (such as AMD Seattle)

So move the dma_map_page() to the .oneinit hook, which executes after the
DMA mask has been set.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:34 +10:00
Ard Biesheuvel
ebf7655aeb drm/nouveau/fb/gf100: defer DMA mapping of scratch page to oneinit() hook
The 100c10 scratch page is mapped using dma_map_page() before the TTM
layer has had a chance to set the DMA mask. This means we are still
running with the default of 32 when this code executes, and this causes
problems for platforms with no memory below 4 GB (such as AMD Seattle)

So move the dma_map_page() to the .oneinit hook, which executes after the
DMA mask has been set.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:33 +10:00
Ben Skeggs
f9c0715e39 drm/nouveau/bar/nv50: fix bar2 vm size
The BAR2 page table was being made WAY too big - oops.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:31 +10:00
Alexandre Courbot
321c258e91 drm/nouveau/volt: use kernel's 64-bit signed division function
Doing direct 64 bit divisions in kernel code leads to references to
undefined symbols on 32 bit architectures. Replace such divisions with
calls to div64_s64 to make the module usable on 32 bit archs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:30 +10:00
Karol Herbst
ebaf3e70aa drm/nouveau/fb/ram: Use Kepler implementation on Maxwell
This enables memory reclocking on Maxwell. Sadly without a PMU firmware it
is useless for gm20x gpus.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:28 +10:00
Karol Herbst
114653c759 drm/nouveau/volt: Make use of cvb coefficients
I'm quite sure that those coefficients are real close, because while
testing the biggest error compared to nvidia was around -1.5% (biggest
error with right coefficients is 12.5mV / 600mV = 2%).

These coefficients were REed by modifing the voltage map entries and by
calculating the set voltage back until I was able to forecast which voltage
nvidia sets for a given voltage map entry.

With these formulars I am able to precisely predict at which exact
temperature Nvidia down- or upvolts due to a changed therm reading.

That's why I am quite sure these are right, or at least really really
close.

v4: Use better coefficients and speedo.
v5: Add error message when speedo is missing.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:28 +10:00
Karol Herbst
08de5743db drm/nouveau/volt/gf100-: Add speedo
v5: Squashed speedo related commits.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:27 +10:00
Karol Herbst
a3c950f2ac drm/nouveau/volt: Add implementation for gf100
Since gf100 we need a speedo value for calculating the voltage. The readout
will be added in a later patch.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:26 +10:00
Karol Herbst
5c3b16ee1d drm/nouveau/bios/vmap: unk0 field is the mode
Depending on the value a different formular is used to calculated the
voltage for this entry.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:26 +10:00
Karol Herbst
5e00e3263b drm/nouveau/volt: Don't require perfect fit
If we calculate the voltage in the table right, we get all kinds of values,
which never fit the hardware steps, so we use the closest higher value the
hardware can do.

v3: Simplify the implementation.
v5: Initialize best_err with volt->max_uv.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:25 +10:00
Karol Herbst
4b9ce6e7b6 drm/nouveau/clk: Allow boosting only when NvBoost is set
0: base clock from the vbios is max clock (default)
1: boost only to boost clock from the vbios
2: boost to max clock available

v2: Moved into nvkm_cstate_valid.
v4: Check the existence of the clocks before limiting.
v5: Default to boost level 0.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:25 +10:00
Karol Herbst
f26493d22f drm/nouveau/bios: Add parsing of VPSTATE table
This table contains three important clocks:

base  clock: This is the non boosted max clock.
tdp   clock: The clock at wich the vbios guarentees the TDP won't ever be
             exceeded at max load (seems to be always the same as the base
             clock, but behaves differently).
boost clock: The avg clock the gpu will stay boosted to. It doesn't seem to
             affect the behaviour of the nvidia driver at all though.

v2: Make clear that base/boost/tdp fields are ids.
v5: Rename Base clock to vpstate.
    Make vbios pointers 32bit.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:24 +10:00
Karol Herbst
1f7f3d91ad drm/nouveau/clk: Respect voltage limits in nvkm_cstate_prog
We should never allow to select a cstate which current voltage (depending
on the temperature) is higher than

1. the max volt entries in the voltage map table.
2. what tha gpu actually can volt to.

v3: Use find_best for all cstates before actually trying.
    Add nvkm_cstate_get function to get cstate by index.
v5: Cstates with voltages lower then min_uv are valid.
    Move nvkm_cstate_get into the previous commit.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:24 +10:00
Karol Herbst
0d6f81003e drm/nouveau/clk: Fixup cstate selection
Now the cstatei parameter can be used of the nvkm_cstate_prog function to
select a specific cstate.

v5: Make a constant for the magic value.
    Use list_last_entry.
    Add nvkm_cstate_get here instead of in the next commit.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:23 +10:00
Karol Herbst
8d08c264d2 drm/nouveau/volt: Add temperature parameter to nvkm_volt_map
The voltage entries actually may map to a different voltage depending on
the current temperature.

v2: Only read the temperature when actually needed.
v5: Be smarter about using max().
    Don't read the temperature anymore.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:23 +10:00
Karol Herbst
61a8b84f1c drm/nouveau/clk: Let nvkm_clk_tstate take a temperature value
This way other subdevs can notify the clk subdev about temperature changes
without the need of clk to poll that value.

Also make this function safe to be called from an interrupt handler.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:22 +10:00
Karol Herbst
761c8f69af drm/nouveau/clk: Add index field to nvkm_cstate
It is better to read out the id out of the cstate struct directly instead
of iterating over the list of cstates over and over again. Especially when
we start saving pointers to a nvkm_cstate struct, it makes things easier.

v5: Rename field to id.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:22 +10:00
Karol Herbst
fa6c4d8e2c drm/nouveau/volt: Add min_id parameter to nvkm_volt_set_id
Each pstate has its own voltage map entry like each cstate has.

The voltages of those entries act as a floor value for the currently
selected pstate and nvidia never sets a voltage below them.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:21 +10:00
Karol Herbst
4a4555a7f1 drm/nouveau/volt: Parse the max voltage map entries
There are at least three "max" entries, which specify the max voltage.
Because they are actually normal voltage map entries, they can also be
affected by the temperature.

Nvidia respects those entries and if they get changed, nvidia uses the
lower voltage from all three.

We shouldn't exceed those voltages at any given time.

v2: State what those entries do in the source.
v3: Add the third max entry.
v5: Better describe the entries.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:20 +10:00
Karol Herbst
17d063dbdc drm/nouveau/clk: Don't create cstates with voltages higher than what the gpu can do
nvkm_volt_map_min is a copy of nvkm_volt_map, which always returns the
lowest possible voltage for a cstate.

nvkm_volt_map will get a temperature parameter there later and also fix
the voltage calculation, so that this functions will be completly
different later.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:20 +10:00
Karol Herbst
17f486de6a drm/nouveau/volt: Properly detect entry based voltage tables
There is a field in the voltage table which tells us if the VIDs are taken
from the entries or calculated through the header.

v2: Don't break older versions.
v5: Reverse flag name.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:19 +10:00
Karol Herbst
32dd7f2329 drm/nouveau/bios/volt: Handle voltage table version 0x50 with zeroed header
Some Fermi+ GPUs specify VID information via voltage table entries, rather
than describing them as a range in the header.

The mask may be bigger than 0x1fffff, but this value is already >2V, so it
will be fine for now.

This patch fixes volting issues on those cards enabling them to switch
cstates.

v6: rework message

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:19 +10:00
Karol Herbst
380b1cadb0 drm/nouveau/fb/ramgk104: Touch 0x62c000 only when there is a display engine
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Tested-by: Aidan Epstein <aidan@jmad.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:18 +10:00
Karol Herbst
cc90badd3c drm/nouveau/clk: Fix potential NULL pointer access when there is no fb subdev
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:18 +10:00
Karol Herbst
a8c119a4d0 drm/nouveau/iccsense: Parse the resistors and config the right way
Previously we parsed that table a bit wrong:
1. The entry layout depends on the sensor type used.
2. We have all resitors in one entry for the INA3221.
3. The config is already included in the vbios.

This commit addresses that issue and with that we should be able to read
out the right power consumption for every GPU with a INA209, INA219 and
INA3221.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:02 +10:00
Ilia Mirkin
9936aeeaeb drm/nouveau/nouveau: bios pointers may be unaligned, use proper accessors
This can show up on SPARC or other architectures that don't handle
unaligned accesses. The kernel normally fixes these up, but it shouldn't
have to.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96836
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:02 +10:00
Alexandre Courbot
69b624983f drm/nouveau/ibus/gk20a: use udelay() in interrupt context
gk20a_ibus_init_ibus_ring() can be called from gk20a_ibus_intr(), in
non-interruptible context. Replace use of usleep_range() with udelay().

Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-10-12 17:29:02 +10:00
Krzysztof Kozlowski
00085f1efa dma-mapping: use unsigned long for dma_attrs
The dma-mapping core and the implementations do not change the DMA
attributes passed by pointer.  Thus the pointer can point to const data.
However the attributes do not have to be a bitfield.  Instead unsigned
long will do fine:

1. This is just simpler.  Both in terms of reading the code and setting
   attributes.  Instead of initializing local attributes on the stack
   and passing pointer to it to dma_set_attr(), just set the bits.

2. It brings safeness and checking for const correctness because the
   attributes are passed by value.

Semantic patches for this change (at least most of them):

    virtual patch
    virtual context

    @r@
    identifier f, attrs;

    @@
    f(...,
    - struct dma_attrs *attrs
    + unsigned long attrs
    , ...)
    {
    ...
    }

    @@
    identifier r.f;
    @@
    f(...,
    - NULL
    + 0
     )

and

    // Options: --all-includes
    virtual patch
    virtual context

    @r@
    identifier f, attrs;
    type t;

    @@
    t f(..., struct dma_attrs *attrs);

    @@
    identifier r.f;
    @@
    f(...,
    - NULL
    + 0
     )

Link: http://lkml.kernel.org/r/1468399300-5399-2-git-send-email-k.kozlowski@samsung.com
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Hans-Christian Noren Egtvedt <egtvedt@samfundet.no>
Acked-by: Mark Salter <msalter@redhat.com> [c6x]
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> [cris]
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> [drm]
Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com>
Acked-by: Joerg Roedel <jroedel@suse.de> [iommu]
Acked-by: Fabien Dessenne <fabien.dessenne@st.com> [bdisp]
Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> [vb2-core]
Acked-by: David Vrabel <david.vrabel@citrix.com> [xen]
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> [xen swiotlb]
Acked-by: Joerg Roedel <jroedel@suse.de> [iommu]
Acked-by: Richard Kuo <rkuo@codeaurora.org> [hexagon]
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k]
Acked-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> [s390]
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> [avr32]
Acked-by: Vineet Gupta <vgupta@synopsys.com> [arc]
Acked-by: Robin Murphy <robin.murphy@arm.com> [arm64 and dma-iommu]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-08-04 08:50:07 -04:00
Ben Skeggs
6258cd43cf drm/nouveau/fb/gp104: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
a4a4cf1bff drm/nouveau/secboot/gm200: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
a96def399b drm/nouveau/ltc/gp100: initial support
Due to the GPU preventing us from touching NV_PLTCG_LTCS_LTSS_CBC_BASE,
we cannot provide CBC/ZBC support without signed PMU firmware to handle
the task for us...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
7ff51f8200 drm/nouveau/fb/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
339e32c0ec drm/nouveau/bios/rammap: 32-bit bios pointers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
32341039e0 drm/nouveau/bios/pll: initial support for BIT 'C' version 2
Just enough to get at the PLL table.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
79bf9552e4 drm/nouveau/bios/dp: initial support for 4.2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
45aa4d0774 drm/nouveau/pci/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
be61c54cbe drm/nouveau/mc/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
51012a39ec drm/nouveau/top/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
c73baa831f drm/nouveau/fb/gf100-: allow selection of an alternate big page size
GFxxx/GM1xx support the selection of 64/128KiB big pages globally.

GM2xx supports the same, as well as another mode where the page size
can be selected per-instance.

We default to 128KiB pages (With per-instance for GM200, but the current
code selects 128KiB there already) as the MMU code isn't currently able
to handle otherwise.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
2f96e8e3e0 drm/nouveau/bios: pointers beyond end of first image need special handling
Makes common the code that was previously used by the PMU table parsing,
as it appears other tables need this too.

Not much of an idea what this is all about...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
4d4e9907ff drm/nouveau/bios: guard against out-of-bounds accesses to image
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
86b40432bd drm/nouveau/ltc/gm107-: decode interrupt status to human-readable strings
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Roy Spliet
f8fa2e4b37 drm/nouveau/clk/gf100: Read secondary bypass postdiv when required
v2: fix typo it's -> its

Signed-off-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Roy Spliet
0f7fbb990c drm/nouveau/clk/gf100-: Clean up PLL locking test
Corresponds with GT215. Don't rely on the lock test logic being
unconditionally enabled, and disable test logic when done (presumably
to save power).

v2: Remove warning, nvkm_msec already warns on time-out

Signed-off-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
20560a9a3c drm/nouveau/secboot: lazy-load firmware and be more resilient
Defer the loading of firmware files to the chip-specific part of secure
boot. This allows implementations to retry loading firmware if the first
attempt failed ; for the GM200 implementation, this happens when trying
to reset a falcon, typically in reaction to GR init.

Firmware loading may fail for a variety of reasons, such as the
filesystem where they reside not being ready at init time. This new
behavior allows GR to be initialized the next time we try to use it if
the firmware has become available.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
4f3c15569e drm/nouveau/secboot/gm200: make firmware loading re-callable
Make it possible to call gm20x_secboot_prepare_blobs() several times
after either success or failure without re-building already existing
blobs. The function will now try to load firmware files that have
previously failed before returning success.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
e5da20a88e drm/nouveau/secboot: fix kerneldoc for secure boot structures
Some members were documented in the wrong structure.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Karol Herbst
437bb44d38 drm/nouveau/volt: save the voltage range we are able to set
We shouldn't set voltages below the min or above the max voltage the gpu is
able to set, so save the range for future lookups.

Signed-off-by: Karol Herbst <karolherbst@gmail.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
22b6c9e8fe drm/nouveau/clk/gm20b: add glitchless and DFS support
This patch adds support for advanced features supported by the
Noise-Aware PLL of Maxwell. Glitchless switch allows the PL field to be
updated without disabling the PLL first if the SYNC_MODE bit of the CFG
register is set.

More significantly, DFS allows the PLL to monitor the actual input
voltage and to dynamically lower the output frequency accordingly. This
allows the clock to be more tolerant of lower voltages.

These improvements are only supported for Tegra speedos >= 1.

Also add the voltage table that is suitable for GM20B's NAPLL. This
change needs to be done atomically for the right voltages to be used by
the clock driver.

v2. Fix build on non-Tegra platforms

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
3786c41518 drm/nouveau/clk/gk20a: rename constructor
Strip the _ prefix off the gk20a clock constructor.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
6ed7e74219 drm/nouveau/clk/gk20a: improve MNP programming
Split the MNP programming function into two functions for the cases
where we allow sliding or not, instead of making it take a parameter for
this. This results in less conditionals in the code and makes it easier
to read.

Also make the MNP programming functions take the PLL parameters as
arguments, and move bits of code to more relevant places (previous
programming tended to be just-in-time, which added more conditionnals in
the code).

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
afea21c917 drm/nouveau/clk/gk20a: factorize n_lo computation code
Use a dedicated function instead of always calculating n_lo on the fly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
89d3a912fc drm/nouveau/clk/gk20a: parameterize PLL settings
Make functions manipulating PLL settings take them as an argument,
instead of assuming we want to work on the copy in the gk20a_clk
structure. This makes these functions more flexible, which we will need
in GM20B.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
a9608c9ba9 drm/nouveau/clk/gk20a: add and use MNP programming functions
Add relevant functions to work with the gk20a_pll structure and use them
where they ought to be instead of directly manipulating registers.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
9102240c69 drm/nouveau/clk/gk20a: use nvkm_ functions in slide()
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
d7ca1106d6 drm/nouveau/clk/gk20a: reorganize MNP calculation a bit
Move variables declarations to their actual scope of use, and simplify
code a bit.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
f5f1b06eea drm/nouveau/clk/gk20a: setup slide once during init
Slide setup needs to be performed only once, during init. Also
use the proper parameters for different clock speeds.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
9772605ce8 drm/nouveau/clk/gk20a: properly protect macro argument
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
791eeea2dc drm/nouveau/volt/gm20b: add support for vmin parameter
Chips may be characterized for a minimum voltage. Support this extra
parameter and select the appropriate minimum voltage for the detected
GPU speedo.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
ebe5e526c1 drm/nouveau/volt/gk20a: rename constructor
Strip the _ prefix off the gk20a volt constructor.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
ff318a51bf drm/nouveau/volt/gk20a: constify and name v_scale
Give a name to this constant so we at least get an idea of what it is
for.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Alexandre Courbot
328bee464b drm/nouveau/volt/gk20a: make unused public functions static
Nobody else is using these, so make them private.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
5dfc5dbf65 drm/nouveau/secboot: use nvkm_mc_enable/disable()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
2b80bb74fb drm/nouveau/secboot: use nvkm_mc_intr_mask/unmask()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
8a90b6fe8c drm/nouveau/mc/gk104-: add pmu reset mask
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
9b02baf19f drm/nouveau/mc/gf100-: support for masking interrupts
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
5805bd1e0b drm/nouveau/mc/gt215: support for masking interrupts
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
66adbfb00d drm/nouveau/mc: support for temporarily masking interrupts from a specific device
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
6e09a57899 drm/nouveau/mc: s/intr_mask/intr_stat/
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
3c2a536b0c drm/nouveau/mc: expose device enable/disable separately, as well as reset
There are cases where subdevs need to perform additonal actions around
the master reset, so we want to expost the operations separately.

This commit also adds a flag to the NV_PMC_ENABLE bitfield definitions
which allow skipping the automatic reset() called from core/subdev.c.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
d398119034 drm/nouveau/mc: take nvkm_device as argument to public functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
d6adbe949d drm/nouveau/mc: allow construction of subclassed device
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
3560e1703f drm/nouveau/top: add function to lookup interrupt mask for a given device
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
952eb819e3 drm/nouveau/top: take nvkm_device as argument to public functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-07-14 11:53:25 +10:00
Ben Skeggs
6aa85f1129 drm/nouveau/iccsense: fix memory leak
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-06-15 16:18:28 +10:00
Ben Skeggs
9057c8d750 drm/nouveau/ltc/gm107-: fix typo in the address of NV_PLTCG_LTC0_LTS0_INTR
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2016-06-02 13:53:38 +10:00
Ben Skeggs
bc9139d23f drm/nouveau/bios/disp: fix handling of "match any protocol" entries
As it turns out, a value of 0xff means "any protocol" and not "VGA".

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2016-06-02 13:53:30 +10:00
Ben Skeggs
4d3df19a8e drm/nouveau/bios/pll: check BIT table version before trying to parse it
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
2781c928b1 drm/nouveau/bios/pll: prevent oops when limits table can't be parsed
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
d07a97e939 drm/nouveau/volt/gk104: round up in gk104_volt_set
We always want a equal or higher voltage than the requested ones, otherwise
nouveau undervolts.

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
e976278ad2 drm/nouveau/fb/gm200: setup mmu debug buffer registers at init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
834b21f5e9 drm/nouveau/fb/gk20a,gm20b: setup mmu debug buffer registers at init()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
99c5917253 drm/nouveau/fb/gf100-: allocate mmu debug buffers
Later chipsets require setting this up both in FB and GR, so let's just
move the allocation to FB.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
917d95a86e drm/nouveau/fb: allow chipset-specific actions for oneinit()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
56d06fa29e drm/nouveau/core: remove pmc_enable argument from subdev ctor
These are now specified directly in the MC subdev.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
d85e2a8dd8 drm/nouveau/mc/nv04: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
667e99ab23 drm/nouveau/mc/nv11: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
79360b7d5f drm/nouveau/mc/nv17: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
9199fbdbf8 drm/nouveau/mc/nv50: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
7354902001 drm/nouveau/mc/g84: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
e56f90fe17 drm/nouveau/mc/g98: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
88c0de2cdb drm/nouveau/mc/gt215: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
a6bb38e902 drm/nouveau/mc/gf100: define reset masks + intr cleanup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
33537d6fdc drm/nouveau/mc/gk104: define reset masks + intr cleanup
Engine fields have been removed, as they're specified by PTOP.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
921be10d85 drm/nouveau/mc: implement support for PTOP interrupt routing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
583f8e4ea2 drm/nouveau/mc: implement support for PTOP reset info
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
70b01f07db drm/nouveau/mc: allow for local definition of reset bits
With the addition of PTOP-specified reset bits, it makes more sense to
move the definitions here rather than in individual subdev
implementations.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
6defde5ab3 drm/nouveau/mc: add helper function to handle device reset
This will be later extended to handle PTOP-specified reset masks as well
as the hardcoded ones.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
87f313e6e6 drm/nouveau/mc: rename struct nvkm_mc_intr to nvkm_mc_map
This will also be used to define NV_PMC_ENABLE <-> subdev mappings in an
upcoming commit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
fb3e9c61ca drm/nouveau/top/gk104: initial implementation
Ported from the code currently in engine/fifo/gk104.c.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
5f76f294d1 drm/nouveau/top: initial implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Ben Skeggs
eaebfcc34e drm/nouveau/core: add top plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
2e9a43f901 drm/nouveau/iccsense: configure sensors like nvidia does
v2: rename ina209/ina219 read function

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
5f1f07de41 drm/nouveau/iccsense: split sensor into own struct
v2: add list_del call, reword error message

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
92224e751f drm/nouveau/iccsense: convert to linked list
v2: add list_del calls

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
d03e0f2748 drm/nouveau/iccsense: remove read function
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Karol Herbst
7d28dbae22 drm/nouveau/pmu: be more strict about locking
When we start communicating with the pmu a bit more, the current code is
a real issue. I encountered a dead lock here, while testing my dynamic
reclocking code

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Alexandre Courbot
c6007dc4e5 drm/nouveau/devinit/gf100: make devinit on resume safer
In case of successful suspend, devinit will have to be run and this is
the behavior currently hardcoded. However, as FD bug 94725 suggests,
there might be cases where runtime suspend leaves the GPU powered, and
in such cases devinit should not be run on resume.

On GF100+ we have a reliable way to know whether we need to run devinit.
Use it instead of blindly trusting the flag set by nvkm_devinit_fini().

The code around the NvForcePost also needs to be slightly reworked in
order to keep working.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Dave Airlie <airlied@redhat.com>
Suggested-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Alexandre Courbot
52829d4fab drm/nouveau/clk/gm20b: add basic driver
Add a basic clock driver that reuses the GK20A logic.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:56 +10:00
Alexandre Courbot
42d6e16787 drm/nouveau/clk/gk20a: share reusable structures/functions
Make functions/structures that the GM20B driver will reuse public.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:56 +10:00
Alexandre Courbot
6871b34a04 drm/nouveau/clk/gk20a: set lowest frequency during init()
Err on the safe side by setting the lowest frequency (and thus voltage)
during device init.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:55 +10:00
Alexandre Courbot
2efd390851 drm/nouveau/clk/gk20a: split gk20a_clk_new()
This allows to instanciate drivers that use the same logic as gk20a with
different parameters.

Add a constructor function to allow other chips that inherit from this
clock to easily initialize its members

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:55 +10:00
Alexandre Courbot
195c113773 drm/nouveau/clk/gk20a: abstract pl_to_div
pl_to_div may be done differently depending on the chip. Abstract this
operation so the same logic can be reused for them as well.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:55 +10:00
Alexandre Courbot
a04bc140aa drm/nouveau/clk/gk20a: put mnp values into their own struct
This allows us to read them using one single function and will be handy
to the GM20B driver.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:54 +10:00
Alexandre Courbot
f29cacf159 drm/nouveau/clk/gk20a: emit parent rate as debug message
Most users are probably not interested in this information.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:54 +10:00
Alexandre Courbot
3c0d5d6e11 drm/nouveau/clk/gk20a: only restore divider to 1:1 if needed
Only restore the 1:1 divider if it is not set already. Also use the
proper masks for this operation and add a second write as done in the
Android code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:53 +10:00
Alexandre Courbot
a08c8bae66 drm/nouveau/clk/gk20a: only compute n_lo if needed
n_lo is used if we are going to slide. Compute it only if that condition
succeeds to avoid confusion about future usage of this computation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:53 +10:00
Alexandre Courbot
3a91b9c5ef drm/nouveau/clk/gk20a: fix VCO bit mask
Fix the mask specified to switch to VCO mode was given as an (incorrect)
immediate value. Although the side-effect happens to be the same, this
is clearly incorrect.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:52 +10:00
Alexandre Courbot
e7952eb663 drm/nouveau/clk/gk20a: rename enable/disable functions
gk20a_pllg_disable() is only used in the context of gk20a_clk_fini().
Move its body there and rename _gk20a_pllg_enable() and
_gk20a_pllg_disable() to non-underscored versions.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:52 +10:00
Alexandre Courbot
d865f3c52d drm/nouveau/clk/gk20a: reorganize variables in gk20a_pllg_calc_mnp()
Move some variables declarations to the scope where they are actually
used to make the code easier to follow.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:51 +10:00
Alexandre Courbot
af6313d61a drm/nouveau/clk/gk20a: convert parameters to Khz
Perform computations in Khz instead of Mhz for better precision.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:51 +10:00
Alexandre Courbot
71757abf2e drm/nouveau/volt: add GM20B driver
Add basic GM20B volt driver that reuses the GK20A logic.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:50 +10:00
Alexandre Courbot
4158c9c2bf drm/nouveau/volt/gk20a: split constructor
Split the constructor function so we can reuse the same logic in other
chips.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:50 +10:00
Vince Hsu
0f9520931e drm/nouveau/volt/gk20a: share reusable members & functions
The CVB calculation and voltage setting functions can be reused for the
future chips. So move the declaration to gk20a.h.

Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:49 +10:00
Karol Herbst
b815a2e3f8 drm/nouveau/pmu/fuc: use imm32 in ld/st macros
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:36 +10:00
Karol Herbst
8609cb8ef0 drm/nouveau/pmu/fuc: use the call macro instead of using the call instruction directly
the macro deals with target specific differences and so we should always use
this

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:36 +10:00
Karol Herbst
70d97b5173 drm/nouveau/pmu/fuc: replace mov+sethi with imm32
on gk208+ we can simply mov 32bits, so we should have a single mov there

v2: use or operator instead of add

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:35 +10:00
Karol Herbst
4382e9091c drm/nouveau/pmu/fuc: fix imm32 for gk208+
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:35 +10:00
Alexandre Courbot
e02d586da6 drm/nouveau/instmem/gk20a: add write barrier when releasing DMA object
When using the DMA-API for instmem, we may obtain a write-combined
mapping. For such cases, add a write barrier in
gk20a_instobj_release_dma() to make sure that all writes have reached
memory at this time.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:34 +10:00
Alexandre Courbot
ab08f38cac drm/nouveau/ltc/gf100: use more reasonable timeout value
LTC operations timeout was set to 2ms, which may be too low for devices
that run at very low clocks (e.g. GM20B) and trigger timeout messages.

Set the timeout to the default 2s. Also remove the redundant error
messages since nvkm_wait_msec() will already display a warning.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:31 +10:00
Karol Herbst
b774c40b1c drm/nouveau/bios/extdev: also parse v4.1 table
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14 10:13:26 +10:00
Karol Herbst
b71c089263 drm/nouveau/iccsense: implement for ina209, ina219 and ina3221
based on Martins initial work

v3: fix ina2x9 calculations
v4: don't kmalloc(0), fix the lsb/pga stuff
v5: add a field to tell if the power reading may be invalid
    add nkvm_iccsense_read_all function
    check for the device on the i2c bus

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14 10:13:25 +10:00
Martin Peres
39b7e6e547 drm/nouveau/nvbios/iccsense: add parsing of the SENSE table
Karol Herbst:
v4: don't kmalloc(0)
v5: stricter validation

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14 10:13:25 +10:00
Martin Peres
dc06e366fe drm/nouveau/subdev/iccsense: add new subdev for power sensors
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14 10:13:24 +10:00
Alexandre Courbot
923f1bd27b drm/nouveau/secboot/gm20b: add secure boot support
Add secure boot support for the GM20B chip found in Tegra X1. Secure
boot on Tegra works slightly differently from desktop, notably in the
way the WPR region is set up.

In addition, the firmware bootloaders use a slightly different header
format.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:24 +10:00
Alexandre Courbot
9cc4552149 drm/nouveau/secboot/gm200: add secure-boot support
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the
high-secure falcon.

This work is based on Deepak Goyal's initial port of Secure Boot to
Nouveau.

v2. use proper memory target function

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:23 +10:00
Alexandre Courbot
7d12388a1f drm/nouveau/core: add support for secure boot
On GM200 and later GPUs, firmware for some essential falcons (notably
GR ones) must be authenticated by a NVIDIA-produced signature and
loaded by a high-secure falcon in order to be able to access privileged
registers, in a process known as Secure Boot.

Secure Boot requires building a binary blob containing the firmwares
and signatures of the falcons to be loaded. This blob is then given to
a high-secure falcon running a signed loader firmware that copies the
blob into a write-protected region, checks that the signatures are
valid, and finally loads the verified firmware into the managed falcons
and switches them to privileged mode.

This patch adds infrastructure code to support this process on chips
that require it.

v2:
- The IRQ mask of the PMU falcon was left - replace it with the proper
  irq_mask variable.
- The falcon reset procedure expecting a falcon in an initialized state,
  which was accidentally provided by the PMU subdev. Make sure that
  secboot can manage the falcon on its own.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:22 +10:00
Ben Skeggs
e24c9c44d7 drm/nouveau/bios/devinit: properly handle unknown generic conditions
Upon encountering an unknown condition code, the script interpreter
is supposed to skip 'size' bytes and continue at the next devinit
token.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:17 +10:00
Ben Skeggs
989f578473 drm/nouveau/bios/devinit: rename INIT_DP_CONDITION to INIT_GENERIC_CONDITION
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:17 +10:00
Ben Skeggs
96aedd0ba9 drm/nouveau/ltc/gm107: fix slice intr offset
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:16 +10:00
Alexandre Courbot
a6a0f67ca7 drm/nouveau/devinit/gf100-: detect if BIOS invoked devinit
It is not advisable to perform devinit if it has already been done.
VBIOS will very likely have invoked devinit if the GPU is the primary
graphics device, but there is no accurate way to detect this fact yet.

This patch adds such a method for gf100 and later chips, by means of the
NV_PTOP_SCRATCH1_DEVINIT_COMPLETED bit. This bit is set to 1 by devinit,
and reset to 0 when the GPU is powered.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:16 +10:00
Alexandre Courbot
8fb1240a71 drm/nouveau/devinit/nv50: remove unneeded variable
We never use any nv50-specific member in this nv50_devinit_preinit().

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:15 +10:00
Ben Skeggs
db1eb52846 drm/nouveau: s/gm204/gm200/ in a number of places
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:12 +10:00
Alexandre Courbot
f0db6e3be9 drm/nouveau/ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait
Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register is set. This happened at least
on GM206 when running glmark2-drm.

While we are at it, use the more compact nvkm_wait_msec() to wait for
the bit to clear.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:11:06 +10:00
Linus Torvalds
e3de671dd6 asm-generic changes for 4.5
The asm-generic tree this time contains one series from Nicolas Pitre
 that makes the optimized do_div() implementation from the ARM
 architecture available to all architectures. This also adds stricter
 type checking for callers of do_div, which has uncovered a number
 of bugs in existing code, and fixes up the ones we have found.
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Merge tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pull asm-generic updates from Arnd Bergmann:
 "The asm-generic tree this time contains one series from Nicolas Pitre
  that makes the optimized do_div() implementation from the ARM
  architecture available to all architectures.

  This also adds stricter type checking for callers of do_div, which has
  uncovered a number of bugs in existing code, and fixes up the ones we
  have found"

* tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
  ARM: asm/div64.h: adjust to generic codde
  __div64_32(): make it overridable at compile time
  __div64_const32(): abstract out the actual 128-bit cross product code
  do_div(): generic optimization for constant divisor on 32-bit machines
  div64.h: optimize do_div() for power-of-two constant divisors
  mtd/sm_ftl.c: fix wrong do_div() usage
  drm/mgag200/mgag200_mode.c: fix wrong do_div() usage
  hid-sensor-hub.c: fix wrong do_div() usage
  ti/fapll: fix wrong do_div() usage
  ti/clkt_dpll: fix wrong do_div() usage
  tegra/clk-divider: fix wrong do_div() usage
  imx/clk-pllv2: fix wrong do_div() usage
  imx/clk-pllv1: fix wrong do_div() usage
  nouveau/nvkm/subdev/clk/gk20a.c: fix wrong do_div() usage
2016-01-20 17:30:20 -08:00
Karol Herbst
25c80507dd drm/nouveau/pci: fix check in nvkm_pcie_set_link
v2: remove unneeded pci check

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-01-14 07:56:37 +10:00
Ben Skeggs
a18c91dece drm/nouveau/pmu: prevent falcon from acking interrupts routed to the host
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:30:23 +10:00
Karol Herbst
f68f4c960a drm/nouveau/perf: change pcie speed on pstate change
v2: remove error and only set link for pcie devices
v6: remove check for pcie device

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:23 +10:00
Karol Herbst
d3b378c09c drm/nouveau/perf: add fields for pci speed and width and use it for the pstates
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:22 +10:00
Karol Herbst
c6e2f9bc03 drm/nouveau/bios/perf: parse the pci speed from the bios for tesla and newer cards
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:22 +10:00
Karol Herbst
3aba825ffa drm/nouveau/pci: implement pcie speed change for kepler+
v2: rename functions
v3: remove pcie2 accessors
v6: fix alignement and line width, also remove useless code

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:21 +10:00
Karol Herbst
7c923844bf drm/nouveau/pci: implement pcie speed change for Fermi
v5: don't set kepler func pointers
v6: fix alignment and line length
2016-01-11 11:30:21 +10:00
Karol Herbst
5cca4bdc0d drm/nouveau/pci: implement pcie speed change for tesla
v5: don't set fermi or kepler func pointers
v6: fix alignment
2016-01-11 11:30:20 +10:00
Karol Herbst
bcc19d9bf5 drm/nouveau/pci: implement generic code for pcie speed change
v2: rename and group functions
v4: change copyright information
    move printing of pcie speeds into oneinit,
    rename all pcie functions to nvkm_pcie_*
    don't try to raise the pcie version when no higher one is supported
v5: revert Copyright changes and rename nvkm_pcie_raise_version to nvkm_pcie_set_version
v6: remove some useless pci_is_pcie checks and rework messages

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:20 +10:00
Karol Herbst
28c8060575 drm/nouveau/pci: add gk104 variant
v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:19 +10:00
Karol Herbst
bec4961e2a drm/nouveau/pci: add gf106 variant
v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:19 +10:00
Ben Skeggs
bac34ed635 drm/nouveau/fb/nv50: remove references to "daemon"
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:23 +10:00
Ben Skeggs
547dd2714a drm/nouveau/clk: remove references to "daemon"
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:23 +10:00
Ben Skeggs
cf0912924f drm/nouveau/bios: parse 8.1 Gbps DP link rate
From DCB 4.1 spec.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:22 +10:00
Ben Skeggs
7d2813c437 drm/nouveau/ltc/gm204: split implementation from gm107
Differences from GM10x:
- GM20x LTC count detection differs from GM10x
- GM20x init doesn't require large page size setting

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:21 +10:00
Ben Skeggs
4fb9c3f3e5 drm/nouveau/ltc/gm107: use nvkm_mask to set cbc_ctrl1
resman and nvgpu both do this, presumably for good reason.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:21 +10:00
Ben Skeggs
e3d26d0860 drm/nouveau/ibus/gm204: split implementation from gk104
GM20x doesn't require the priv ring timeout bumps that GK/GM10x have.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:20 +10:00
Alexandre Courbot
b306712d92 drm/nouveau/instmem/gk20a: use DMA API CPU mapping
Commit 69c4938249 ("drm/nouveau/instmem/gk20a: use direct CPU access")
tried to be smart while using the DMA-API by managing the CPU mappings of
buffers allocated with the DMA-API by itself. In doing so, it relied
on dma_to_phys() which is an architecture-private function not
available everywhere. This broke the build on several architectures.

Since there is no reliable and portable way to obtain the physical
address of a DMA-API buffer, stop trying to be smart and just use the
CPU mapping that the DMA-API can provide. This means that buffers will
be CPU-mapped for all their life as opposed to when we need them, but
anyway using the DMA-API here is a fallback for when no IOMMU is
available so we should not expect optimal behavior.

This makes the IOMMU and DMA-API implementations of instmem diverge
enough that we should maybe put them into separate files...

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Alexandre Courbot
338840eed1 drm/nouveau/instmem/gk20a: fix race conditions
The LRU list used for recycling CPU mappings was handling concurrency
very poorly. For instance, if an instobj was acquired twice before being
released once, it would end up into the LRU list even though there is
still a client accessing it.

This patch fixes this by properly counting how many clients are
currently using a given instobj.

While at it, we also raise errors when inconsistencies are detected, and
factorize some code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Ilia Mirkin
cfb4f929f7 drm/nouveau/nvkm: add/remove 0's to make 7 (or 9)-nibble constants use 8 nibbles
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Dave Airlie
6545f31897 Merge branch 'linux-4.4' of git://github.com/skeggsb/linux into drm-fixes
single nouveau fix.

* 'linux-4.4' of git://github.com/skeggsb/linux:
  drm/nouveau/bios/fan: hardcode the fan mode to linear
2015-12-19 13:25:42 +10:00
Martin Peres
a814a29d7b drm/nouveau/bios/fan: hardcode the fan mode to linear
This is an oversight that made use of the trip-point-based fan managenent on
cards that never expose those. This led the fan to stay at fan_min.

Fortunately, the emergency code would kick when the temperature would reach
90°C.

Reported-by: Tom Englund <tomenglund26@gmail.com>
Tested-by: Tom Englund <tomenglund26@gmail.com>
Signed-off-by: Martin Peres <martin.peres@free.fr>
Tested-by: Daemon32 <lnf.purple@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92126
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2015-12-18 09:01:22 +10:00
Dave Airlie
ff6e0fd55e Merge branch 'linux-4.4' of https://github.com/skeggsb/linux into drm-fixes
Just the one commit I mentioned earlier, making the PGOB workaround the
default.

* 'linux-4.4' of https://github.com/skeggsb/linux:
  drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by default
2015-12-09 14:15:58 +10:00