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41 Commits

Author SHA1 Message Date
Fabien Parent
c1ff4e3f40 drm/mediatek: Add DDP support for MT8167 
Add DDP support for MT8167 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
 2020-11-08 00:46:45 +08:00
Enric Balletbo i Serra
2c758e301e soc / drm: mediatek: Move routing control to mmsys device 
Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
Those functions will allow DRM driver and others to control the data
path routing.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2020-04-13 13:01:16 +02:00
Matthias Brugger
af19d64501 drm/mediatek: Omit warning on probe defers 
It can happen that the mmsys clock drivers aren't probed before the
platform driver gets invoked. The platform driver used to print a warning
that the driver failed to get the clocks. Omit this error on
the defered probe path.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2020-04-13 13:01:16 +02:00
CK Hu
631005b255 drm/mediatek: add no_clk into ddp private data 
Mutex has no clock in some SoC, so add no_clk in private data and get
clock according to no_clk.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2019-10-09 16:58:13 +08:00
Yongqiang Niu
1037edf20c drm/mediatek: add mutex sof register offset into ddp private data 
mutex sof register offset will be private data of ddp

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2019-10-09 16:58:13 +08:00
Yongqiang Niu
1c7da0c762 drm/mediatek: add mutex sof into ddp private data 
mutex sof will be ddp private data

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2019-10-09 16:58:13 +08:00
Yongqiang Niu
d730af989e drm/mediatek: add mutex mod register offset into ddp private data 
mutex mod register offset will be private data of ddp.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2019-10-09 16:58:12 +08:00
Yongqiang Niu
0d3a120286 drm/mediatek: add mutex mod into ddp private data 
except mutex mod, mutex mod reg,mutex sof reg,
and mutex sof id will be ddp private data

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2019-10-09 16:58:12 +08:00
Thomas Gleixner
1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2019-05-30 11:26:41 -07:00
Bibby Hsieh
014e604196 drm/mediatek: implement connection from BLS to DPI0 
Modify display driver to support connection from BLS to DPI.

Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-10-03 11:56:33 +08:00
Stu Hsieh
08bcbed747 drm/mediatek: fix connection from RDMA2 to DSI1 
This patch fix connection from RDMA2 to DSI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-08-27 11:24:37 +08:00
Stu Hsieh
85186efc2a drm/mediatek: add connection from RDMA2 to DSI0 
This patch add connection from RDMA2 to DSI0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-08-27 11:24:35 +08:00
Stu Hsieh
0a14785ee3 drm/mediatek: add connection from RDMA1 to DSI0 
This patch add connection from RDMA1 to DSI0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-08-27 11:24:35 +08:00
Stu Hsieh
48d25d243b drm/mediatek: add connection from RDMA0 to DSI1 
This patch add connection from RDMA0 to DSI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-08-27 11:24:35 +08:00
Stu Hsieh
29d32e466e drm/mediatek: add connection from RDMA0 to DPI1 
This patch add connection from RDMA0 to DPI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-08-27 11:24:35 +08:00
stu.hsieh@mediatek.com
e6ab087a22 drm/mediatek: Add support for mediatek SOC MT2712 
This patch add support for the Mediatek MT2712 DISP subsystem.
There are two OVL engine and three disp output in MT2712.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-28 00:27:36 +08:00
stu.hsieh@mediatek.com
16dd757ead drm/mediatek: add DSI3 support for mutex 
This patch add the DSI3 support for mutex

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:08:44 +08:00
stu.hsieh@mediatek.com
dee8eb4e66 drm/mediatek: add DSI2 support for mutex 
This patch add the DSI2 support for mutex

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:08:29 +08:00
stu.hsieh@mediatek.com
f4f3ec480e drm/mediatek: add DPI1 support for mutex 
This patch add the DPI1 support for mutex

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:08:12 +08:00
stu.hsieh@mediatek.com
d335369e75 drm/mediatek: add connection from RDMA2 to DSI3 
This patch add the connection from RDMA2 to DSI3

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:07:51 +08:00
stu.hsieh@mediatek.com
46ce9b2dc7 drm/mediatek: add connection from RDMA2 to DSI2 
This patch add the connection from RDMA2 to DSI2

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:07:34 +08:00
stu.hsieh@mediatek.com
0064be8c71 drm/mediatek: add connection from RDMA2 to DSI1 
This patch add the connection from RDMA2 to DSI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:07:19 +08:00
stu.hsieh@mediatek.com
7ddac09167 drm/mediatek: add connection from RDMA2 to DPI1 
This patch add the connection from RDMA2 to DPI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:07:02 +08:00
stu.hsieh@mediatek.com
01915b8588 drm/mediatek: add connection from RDMA2 to DPI0 
This patch add the connection from RDMA2 to DPI0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:06:48 +08:00
stu.hsieh@mediatek.com
15484ae0af drm/mediatek: add connection from RDMA1 to DSI3 
This patch add the connection from RDMA1 to DSI3

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:06:30 +08:00
stu.hsieh@mediatek.com
5346010f72 drm/mediatek: add connection from RDMA1 to DSI2 
This patch add the connection from RDMA1 to DSI2

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:06:14 +08:00
stu.hsieh@mediatek.com
d46a8f851e drm/mediatek: add connection from RDMA1 to DSI1 
This patch add the connection from RDMA1 to DSI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:05:56 +08:00
stu.hsieh@mediatek.com
73fabd5ceb drm/mediatek: add connection from RDMA1 to DPI1 
This patch add the connection from RDMA1 to DPI1

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:05:39 +08:00
stu.hsieh@mediatek.com
89c04d6502 drm/mediatek: add connection from RDMA0 to DSI3 
This patch add the connection from RDMA0 to DSI3

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:05:23 +08:00
stu.hsieh@mediatek.com
49793b7674 drm/mediatek: add connection from RDMA0 to DSI2 
This patch add the connection from RDMA0 to DSI2

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:05:06 +08:00
stu.hsieh@mediatek.com
7b86302401 drm/mediatek: add connection from RDMA0 to DPI0 
This patch add the connection from RDMA0 to DPI0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:04:50 +08:00
stu.hsieh@mediatek.com
09013b1619 drm/mediatek: Update the definition of connection from RDMA1 to DPI0 
This patch update the definition of connection from RDMA1 to DPI0.
Change the term MOUT to SOUT.

Because our HW datasheet use the term SOUT to match its function for RDMA.
For consistency, changing the name from MOUT to SOUT is better.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:04:30 +08:00
stu.hsieh@mediatek.com
9b7b38de38 drm/mediatek: add connection from OD1 to RDMA1 
This patch add the connection from OD1 to RDMA1 for ext path.

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:04:11 +08:00
stu.hsieh@mediatek.com
df2dce4e11 drm/mediatek: add ddp component OD1 
This patch add the component OD1 and
rename the OD to OD0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:01:48 +08:00
stu.hsieh@mediatek.com
d480bbc474 drm/mediatek: add ddp component AAL1 
This patch add component AAL1 and
rename AAL to AAL0

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:01:22 +08:00
stu.hsieh@mediatek.com
8617ec2474 drm/mediatek: support maximum 64 mutex mod 
This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
 2018-06-24 12:00:27 +08:00
yt.shen@mediatek.com
84a5ead18e drm/mediatek: add support for Mediatek SoC MT2701 
This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
 2017-04-08 00:02:17 +08:00
yt.shen@mediatek.com
fb2557de27 drm/mediatek: update display module connections 
update connections for OVL, RDMA, BLS, DSI

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
 2017-04-08 00:02:14 +08:00
yt.shen@mediatek.com
9dc84e98a3 drm/mediatek: add shadow register support 
We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
 2017-04-08 00:02:13 +08:00
yt.shen@mediatek.com
c5f228ef6c drm/mediatek: add *driver_data for different hardware settings 
There are some hardware settings changed, between MT8173 & MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
MIPI_TX pll setting changed.
And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
 2017-04-08 00:02:12 +08:00
CK Hu
119f517362 drm/mediatek: Add DRM Driver for Mediatek SoC MT8173. 
This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Mao Huang <littlecvr@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
 2016-05-06 17:47:35 +02:00