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1af7e7f8c12f521c111bd7cf0d138be7e15b51a5
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3 Commits

Author SHA1 Message Date
Dmitry Baryshkov
5047ab95bb drm/msm/dsi_pll_7nm: restore VCO rate during restore_state 
PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d14 ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2020-11-04 08:26:25 -08:00
Rob Clark
200a2186b6 drm/msm: fix 32b build warns 
Neither of these code-paths apply to older 32b devices, but it is rude
to introduce warnings.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200929001925.2916984-1-robdclark@gmail.com
 2020-09-29 10:20:51 +10:00
Jonathan Marek
1ef7c99d14 drm/msm/dsi: add support for 7nm DSI PHY/PLL 
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250.

Implementation is based on 10nm driver, but updated based on the downstream
7nm driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250)
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2020-09-12 09:59:58 -07:00