Chris Wilson
1a53924792
drm/i915/selftests: Measure CS_TIMESTAMP
...
Count the number of CS_TIMESTAMP ticks and check that it matches our
expectations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200521071059.31726-1-chris@chris-wilson.co.uk
2020-05-21 09:30:16 +01:00
Chris Wilson
6dc0d028f5
drm/i915/gt: Fix up clock frequency
...
The bspec lists both the clock frequency and the effective interval. The
interval corresponds to observed behaviour, so adjust the frequency to
match.
v2: Mika rightfully asked if we could measure the clock frequency from a
selftest.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200427154554.12736-1-chris@chris-wilson.co.uk
2020-04-27 17:34:33 +01:00
Chris Wilson
e42a969e72
drm/i915/selftests: Exercise dynamic reclocking with RPS
...
After having testing all the RPS controls individually, we need to take
a step back and check how our RPS worker integrates them to perform
dynamic GPU reclocking. So do that by submitting a spinner and wait and
see what happens.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200420172739.11620-6-chris@chris-wilson.co.uk
2020-04-20 20:08:07 +01:00
Chris Wilson
0eaccc4b18
drm/i915/selftests: Split RPS frequency measurement
...
Split the frequency measurement into two modes, so that we can judge the
impact of the llc setup on top of the pure CS frequency scaling.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200420172739.11620-4-chris@chris-wilson.co.uk
2020-04-20 20:08:07 +01:00
Chris Wilson
9938ee2e63
drm/i915/selftests: Check RPS controls
...
Check that the GPU does respond to our RPS frequency requests by setting
our desired frequency.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200420172739.11620-3-chris@chris-wilson.co.uk
2020-04-20 20:08:06 +01:00
Chris Wilson
4ba74e53ad
drm/i915/selftests: Verify frequency scaling with RPS
...
One of the core tenents of reclocking the GPU is that its throughput
scales with the clock frequency. We can observe this by incrementing a
loop counter on the GPU, and compare the different execution rates at
the notional RPS frequencies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200420172739.11620-1-chris@chris-wilson.co.uk
2020-04-20 20:08:06 +01:00
Chris Wilson
c43dd6b414
drm/i915/selftests: Check power consumption at min/max frequencies
...
A basic premise of RPS is that at lower frequencies, not only do we run
slower, but we save power compared to higher frequencies. For example,
when idle, we set the minimum frequency just in case there is some
residual current. Since the power curve should be a physical
relationship, if we find no power saving it's likely that we've broken
our frequency handling, so test!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Andi Shyti <andi.shyti@intel.com >
Reviewed-by: Andi Shyti <andi.shyti@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200417152018.13079-2-chris@chris-wilson.co.uk
2020-04-17 18:48:51 +01:00
Chris Wilson
46495adc6c
drm/i915/selftests: Exercise basic RPS interrupt generation
...
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Andi Shyti <andi.shyti@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20200415170318.16771-1-chris@chris-wilson.co.uk
2020-04-16 00:21:18 +01:00
Chris Wilson
730eaeb524
drm/i915/gt: Manual rc6 entry upon parking
...
Now that we rapidly park the GT when the GPU idles, we often find
ourselves idling faster than the RC6 promotion timer. Thus if we tell
the GPU to enter RC6 manually as we park, we can do so quicker (by
around 50ms, half an EI on average) and marginally increase our
powersaving across all execlists platforms.
v2: Now with a selftest to check we can enter RC6 manually
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Andi Shyti <andi.shyti@intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Imre Deak <imre.deak@intel.com >
Acked-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Andi Shyti <andi.shyti@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20191127095657.3209854-1-chris@chris-wilson.co.uk
2019-11-27 12:53:27 +00:00
Chris Wilson
ba446f7460
drm/i915/selftests: Exercise rc6 w/a handling
...
Reading from CTX_INFO upsets rc6, requiring us to detect and prevent
possible rc6 context corruption. Poke at the bear!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Imre Deak <imre.deak@intel.com >
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Reviewed-by: Andi Shyti <andi.shyti@intel.com >
Tested-by: Andi Shyti <andi.shyti@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20191119154723.3311814-1-chris@chris-wilson.co.uk
2019-11-19 20:05:01 +00:00
Chris Wilson
833e979db3
drm/i915/selftests: Add intel_gt_suspend_prepare
...
Call suspend_prepare first so that we don't leave GuC so confused.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Acked-by: Andi Shyti <andi.shyti@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20191101174405.7389-1-chris@chris-wilson.co.uk
2019-11-01 18:52:23 +00:00
Chris Wilson
c601cb2135
drm/i915: Defer rc6 shutdown to suspend_late
...
Currently we shutdown rc6 during i915_gem_resume() but this is called
during the preparation phase (i915_drm_prepare) for all suspend paths,
but we only want to shutdown rc6 for S3+. Move the actual shutdown to
i915_gem_suspend_late().
We then need to differentiate between suspend targets, to distinguish S0
(s2idle) where the device is kept awake but needs to be in a low power
mode (the same as runtime suspend) from the device suspend levels where
we lose control of HW and so must disable any HW access to dangling
memory.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111909
Fixes: c113236718chris@chris-wilson.co.uk >
Cc: Andi Shyti <andi.shyti@intel.com >
Acked-by: Andi Shyti <andi.shyti@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20191101141009.15581-4-chris@chris-wilson.co.uk
2019-11-01 14:47:36 +00:00
Andi Shyti
0dc3c562aa
drm/i915: Extract GT ring management
...
Although the ring management is much smaller compared to the other GT
power management functions, continue the theme of extracting it out of
the huge intel_pm.c for maintenance.
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti <andi.shyti@intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20191020184139.9145-1-chris@chris-wilson.co.uk
2019-10-20 20:45:18 +01:00
Andi Shyti
c113236718
drm/i915: Extract GT render sleep (rc6) management
...
Continuing the theme of breaking intel_pm.c up in a reasonable chunk of
powermanagement utilities, pull out the rc6 setup into its GT handler.
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti <andi.shyti@intel.com >
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: https://patchwork.freedesktop.org/patch/msgid/20190919143840.20384-1-andi.shyti@intel.com
Link: https://patchwork.freedesktop.org/patch/msgid/20190927110849.28734-1-chris@chris-wilson.co.uk
2019-09-27 13:01:57 +01:00
