Forbid splitting VVAR VMA resulting in a stricter ABI and reducing the
amount of corner-cases to consider while working further on VDSO time
namespace support.
As the offset from timens to VVAR page is computed compile-time, the pages
in VVAR should stay together and not being partically mremap()'ed.
Signed-off-by: Andrei Vagin <avagin@gmail.com>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Dmitry Safonov <dima@arista.com>
Link: https://lore.kernel.org/r/20200624083321.144975-6-avagin@gmail.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
If a task belongs to a time namespace then the VVAR page which contains
the system wide VDSO data is replaced with a namespace specific page
which has the same layout as the VVAR page.
Signed-off-by: Andrei Vagin <avagin@gmail.com>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Dmitry Safonov <dima@arista.com>
Link: https://lore.kernel.org/r/20200624083321.144975-5-avagin@gmail.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add SMMU support for the Marvell AP806 based SoCs (Armada 70xx and
Armada 80xx)
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Merge tag 'mvebu-dt64-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt
mvebu dt64 for 5.9 (part 1)
Add SMMU support for the Marvell AP806 based SoCs (Armada 70xx and
Armada 80xx)
* tag 'mvebu-dt64-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: add SMMU support
- Add platforms chipid nodes for am65x and j721e
- Update latest data sheet values for MMC on am65x
- Add serdes and usb3 support for j721e
- Add analog audio support for j721e
- Add SD card support for am65x
- Rename DT nodes for gic-its/smmu to their standard counterparts am65x/j721e
- HTTP links replaced with HTTPS ones
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Merge tag 'ti-k3-dt-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt
Texas Instruments K3 SoC DT updates for v5.9
- Add platforms chipid nodes for am65x and j721e
- Update latest data sheet values for MMC on am65x
- Add serdes and usb3 support for j721e
- Add analog audio support for j721e
- Add SD card support for am65x
- Rename DT nodes for gic-its/smmu to their standard counterparts am65x/j721e
- HTTP links replaced with HTTPS ones
* tag 'ti-k3-dt-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line
arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0
arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX
arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux
arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes
dt-bindings: mfd: ti,j721e-system-controller.yaml: Add J721e system controller
arm64: dts: ti: k3-am65/j721e-main: rename gic-its node to msi-controller
arm64: dts: ti: k3-j721e-main: rename smmu node to iommu
arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones
arm64: dts: ti: k3-am654-base-board: Add support for SD card
arm64: dts: ti: k3-am65-main: Add support for sdhci1
arm64: dts: ti: j721e-common-proc-board: Analog audio support
arm64: dts: ti: k3-j721e-common-proc-board: Remove duplicated main_i2c1_exp4_pins_default
arm64: dts: ti: k3-am654-main: Update otap-del-sel values
arm64: dts: ti: k3-j721e-mcu-wakeup: add k3 platforms chipid module node
arm64: dts: ti: k3-am65-wakeup: add k3 platforms chipid module node
Link: https://lore.kernel.org/r/3b3b9214-769d-ba1b-db5e-44414a8c5756@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds the initial support for the Amazon's Annapurna Labs
Alpine v3 Soc and Evaluation Platform (EVP).
Link: https://lore.kernel.org/r/20200724132654.16549-7-hhhawa@amazon.com
Signed-off-by: Ronen Krupnik <ronenk@amazon.com>
Signed-off-by: Talel Shenhar <talel@amazon.com>
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As preparation to add device tree binding for Amazon's Annapurna Labs
Alpine v3 support. Rename al device tree folder to be amazon.
Link: https://lore.kernel.org/r/20200724132654.16549-3-hhhawa@amazon.com
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Allocate the time namespace page among VVAR pages. Provide
__arch_get_timens_vdso_data() helper for VDSO code to get the
code-relative position of VVARs on that special page.
If a task belongs to a time namespace then the VVAR page which contains
the system wide VDSO data is replaced with a namespace specific page
which has the same layout as the VVAR page. That page has vdso_data->seq
set to 1 to enforce the slow path and vdso_data->clock_mode set to
VCLOCK_TIMENS to enforce the time namespace handling path.
The extra check in the case that vdso_data->seq is odd, e.g. a concurrent
update of the VDSO data is in progress, is not really affecting regular
tasks which are not part of a time namespace as the task is spin waiting
for the update to finish and vdso_data->seq to become even again.
If a time namespace task hits that code path, it invokes the corresponding
time getter function which retrieves the real VVAR page, reads host time
and then adds the offset for the requested clock which is stored in the
special VVAR page.
The time-namespace page isn't allocated on !CONFIG_TIME_NAMESPACE, but
vma is the same size, which simplifies criu/vdso migration between
different kernel configs.
Signed-off-by: Andrei Vagin <avagin@gmail.com>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Dmitry Safonov <dima@arista.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20200624083321.144975-4-avagin@gmail.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The order of vvar pages depends on whether a task belongs to the root
time namespace or not. In the root time namespace, a task doesn't have a
per-namespace page. In a non-root namespace, the VVAR page which contains
the system-wide VDSO data is replaced with a namespace specific page
that contains clock offsets.
Whenever a task changes its namespace, the VVAR page tables are cleared
and then they will be re-faulted with a corresponding layout.
A task can switch its time namespace only if its ->mm isn't shared with
another task.
Signed-off-by: Andrei Vagin <avagin@gmail.com>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Dmitry Safonov <dima@arista.com>
Reviewed-by: Christian Brauner <christian.brauner@ubuntu.com>
Link: https://lore.kernel.org/r/20200624083321.144975-3-avagin@gmail.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Currently the vdso has no awareness of time namespaces, which may
apply distinct offsets to processes in different namespaces. To handle
this within the vdso, we'll need to expose a per-namespace data page.
As a preparatory step, this patch separates the vdso data page from
the code pages, and has it faulted in via its own fault callback.
Subsquent patches will extend this to support distinct pages per time
namespace.
The vvar vma has to be installed with the VM_PFNMAP flag to handle
faults via its vma fault callback.
Signed-off-by: Andrei Vagin <avagin@gmail.com>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Dmitry Safonov <dima@arista.com>
Link: https://lore.kernel.org/r/20200624083321.144975-2-avagin@gmail.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
While MTE is not supported in the upstream kernel yet, add a comment
that HWCAP2_MTE as (1 << 18) is reserved. Glibc makes use of it for the
resolving (ifunc) of the MTE-safe string routines.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
SOM and it's Rock Pi N8 icarnation. This brings some arm64 dts-changes
with it as the underlying Dalang carrier board is shared by both
an arm32 rk3288 SOM and an arm64 rk3399 SOM (Rock Pi N10).
Other than that rk3288 gets its ohci node added that only works
on the fixed rk3288w variant of the soc and some asorted fixes
and improvements for dt-binding-check.
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Merge tag 'v5.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Biggest part is the addition of the rk3288 variant of the VMARC
SOM and it's Rock Pi N8 icarnation. This brings some arm64 dts-changes
with it as the underlying Dalang carrier board is shared by both
an arm32 rk3288 SOM and an arm64 rk3399 SOM (Rock Pi N10).
Other than that rk3288 gets its ohci node added that only works
on the fixed rk3288w variant of the soc and some asorted fixes
and improvements for dt-binding-check.
* tag 'v5.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add PCIe for RockPI N10
ARM: dts: rockchip: Add HDMI out for RockPI N8/N10
ARM: dts: rockchip: Add USB for RockPI N8/N10
ARM: dts: rockchip: Add usb host0 ohci node for rk3288
ARM: dts: rockchip: Fix VBUS on rk3288-vyasa
ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support
ARM: dts: rockchip: Add VMARC RK3288 SOM initial support
dt-bindings: arm: rockchip: Add Rock Pi N8 binding
arm64: dts: rk3399pro: vmarc-som: Move common properties into Carrier
arm64: dts: rk3399pro: vmarc-som: Move supply regulators into Carrier
arm64: dts: rk3399pro: vmarc-som: Fix sorting nodes, properties
ARM: dts: rockchip: dalang-carrier: Move i2c nodes into SOM
ARM: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac
ARM: dts: rockchip: Add marvell BT irq config
ARM: dts: rockchip: rename label and nodename pinctrl subnodes that end with gpio
Link: https://lore.kernel.org/r/2472314.kD9Egx1jfM@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
first tiny part of the rk3399 camera infrastructure and cleanups + making
dt-binding-check even happier.
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Merge tag 'v5.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Fuel gauge for Pinebook Pro, the newly added periph-burst flag for pl330s,
first tiny part of the rk3399 camera infrastructure and cleanups + making
dt-binding-check even happier.
* tag 'v5.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac
arm64: dts: rockchip: remove bus-width from mmc nodes in px30 dts files
arm64: dts: rockchip: add rx0 mipi-phy for rk3399
arm64: dts: rockchip: rename and label gpio-led subnodes part 2
arm64: dts: rockchip: rename label and nodename pinctrl subnodes that end with gpio
arm64: dts: rockchip: fix rk3399-puma gmac reset gpio
arm64: dts: rockchip: fix rk3399-puma vcc5v0-host gpio
arm64: dts: rockchip: fix rk3368-lion gmac reset gpio
arm64: dts: rockchip: set rockpro64 usbc dr_mode as host
arm64: dts: rockchip: add fuel gauge to Pinebook Pro dts
Link: https://lore.kernel.org/r/2221560.KYr1Tee2JR@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Factor the 12 copies of the SW PAN entry and exit code into callable
subroutines, and use alternatives patching to either emit a 'bl'
instruction to call them, or a NOP if h/w PAN is found to be available
at runtime.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20200721083315.4816-1-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Newer versions of clang only look for $(COMPAT_GCC_TOOLCHAIN_DIR)as [1],
rather than $(COMPAT_GCC_TOOLCHAIN_DIR)$(CROSS_COMPILE_COMPAT)as,
resulting in the following build error:
$ make -skj"$(nproc)" ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- \
CROSS_COMPILE_COMPAT=arm-linux-gnueabi- LLVM=1 O=out/aarch64 distclean \
defconfig arch/arm64/kernel/vdso32/
...
/home/nathan/cbl/toolchains/llvm-binutils/bin/as: unrecognized option '-EL'
clang-12: error: assembler command failed with exit code 1 (use -v to see invocation)
make[3]: *** [arch/arm64/kernel/vdso32/Makefile:181: arch/arm64/kernel/vdso32/note.o] Error 1
...
Adding the value of CROSS_COMPILE_COMPAT (adding notdir to account for a
full path for CROSS_COMPILE_COMPAT) fixes this issue, which matches the
solution done for the main Makefile [2].
[1]: 3452a0d8c1
[2]: https://lore.kernel.org/lkml/20200721173125.1273884-1-maskray@google.com/
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Cc: stable@vger.kernel.org
Link: https://github.com/ClangBuiltLinux/linux/issues/1099
Link: https://lore.kernel.org/r/20200723041509.400450-1-natechancellor@gmail.com
Signed-off-by: Will Deacon <will@kernel.org>
- Update SCU irq code to call pm_system_wakeup() in general MU IRQ
handler, so that system can be waked up when MU IRQ arrives.
- Move i.MX SCU soc driver into imx firmware folder to get it
initialized from i.MX SCU firmware driver.
- Clean up soc-imx-scu driver a bit by using devm_kasprintf().
- Correct postfix setting for cm40 power domain in scu-pd driver.
- Add resource management support for IMX_SCU firmware driver.
- Add more cm4 resources to i.MX SCU power domain driver.
- Select ARM_GIC_V3 from SOC_IMX8M for being able to use GICv3 driver
in AARCH32 mode Linux on AARCH64 hardware.
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Merge tag 'imx-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers change for 5.9:
- Update SCU irq code to call pm_system_wakeup() in general MU IRQ
handler, so that system can be waked up when MU IRQ arrives.
- Move i.MX SCU soc driver into imx firmware folder to get it
initialized from i.MX SCU firmware driver.
- Clean up soc-imx-scu driver a bit by using devm_kasprintf().
- Correct postfix setting for cm40 power domain in scu-pd driver.
- Add resource management support for IMX_SCU firmware driver.
- Add more cm4 resources to i.MX SCU power domain driver.
- Select ARM_GIC_V3 from SOC_IMX8M for being able to use GICv3 driver
in AARCH32 mode Linux on AARCH64 hardware.
* tag 'imx-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: select ARM_GIC_V3 for i.MX8M
firmware: imx: Move i.MX SCU soc driver into imx firmware folder
firmware: imx: scu-pd: add more cm4 resources
firmware: imx: add resource management api
firmware: imx: scu-pd: fix cm40 power domain
soc: imx: scu: use devm_kasprintf
firmware: imx: make sure MU irq can wake up system from suspend mode
Link: https://lore.kernel.org/r/20200720085536.24138-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).
Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for the Microchip Sparx5 ARMv8-based SoC family of
TSN-capable gigabit switches.
Link: https://lore.kernel.org/r/20200615133242.24911-3-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Enable UFS (Universal Flash Storage) on Exynos7 Espresso board.
2. Fix silent hang after boot off Exynos7 Espresso board.
3. Minor DTS fixes and adjustments with dtschema.
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Merge tag 'samsung-dt64-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.9
1. Enable UFS (Universal Flash Storage) on Exynos7 Espresso board.
2. Fix silent hang after boot off Exynos7 Espresso board.
3. Minor DTS fixes and adjustments with dtschema.
* tag 'samsung-dt64-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add unit address to soc node and move thermal zones on Exynos7
arm64: dts: exynos: Add unit address to soc node on Exynos5433
arm64: dts: exynos: Remove DMA controller bus node name to fix dtschema warnings
arm64: dts: exynos: Keep LDO12 always-on on Espresso
arm64: dts: exynos: Fix silent hang after boot on Espresso
arm64: dts: exynos: Remove generic arm,armv8-pmuv3 compatible
arm64: dts: exynos: Describe PWM interrupts on Exynos7
arm64: dts: exynos: Add UFS node to Exynos7
Link: https://lore.kernel.org/r/20200721180900.13844-3-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
For SM8250 this adds the main pinctrl/gpio block (TLMM), I2C and SPI
controllers, the CPU subsytem watchdog, inter-processor signalling
controller (IPCC), always-on power/clock controller (AOSS),
inter-processor state machine (SMP2P), defines remoteproc controls
for audio, compute and sensor processors and base definition for the
PM8009 PMIC. It also does fix up a few minor issues from the initial
merge of the platform support.
SC7180 and SDM845 gains interconnect paths and performance tables
defined for display, QUP, QSPI, SDHC and CPUs.
SC7180 gains WiFi support and some cleanups related to the modem
remoteproc.
SDM845 gains inline crypto engine support for UFS, LAB/IBB
regulators for powering display panels, remoteproc relocation debug
support
SM8150 gains USB controller support and the two related PHYs, as well as
thermal zones and throttling support.
IPQ8074 gains USB and SDHCI support.
MSM8916 is being cleaned up, gains interconnect providers and Samsung
A2015 gains accelerometer and magnetometer support.
MSM8994 gains PSCI, SDHCI, SPMI support, I2C, SPI, UART gains DMA
support and the DTS files are cleaned up.
The SDM630 platform DTS is at last merged and initial support for Sony
Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra is added.
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Merge tag 'qcom-arm64-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DT updates for v5.9
For SM8250 this adds the main pinctrl/gpio block (TLMM), I2C and SPI
controllers, the CPU subsytem watchdog, inter-processor signalling
controller (IPCC), always-on power/clock controller (AOSS),
inter-processor state machine (SMP2P), defines remoteproc controls
for audio, compute and sensor processors and base definition for the
PM8009 PMIC. It also does fix up a few minor issues from the initial
merge of the platform support.
SC7180 and SDM845 gains interconnect paths and performance tables
defined for display, QUP, QSPI, SDHC and CPUs.
SC7180 gains WiFi support and some cleanups related to the modem
remoteproc.
SDM845 gains inline crypto engine support for UFS, LAB/IBB
regulators for powering display panels, remoteproc relocation debug
support
SM8150 gains USB controller support and the two related PHYs, as well as
thermal zones and throttling support.
IPQ8074 gains USB and SDHCI support.
MSM8916 is being cleaned up, gains interconnect providers and Samsung
A2015 gains accelerometer and magnetometer support.
MSM8994 gains PSCI, SDHCI, SPMI support, I2C, SPI, UART gains DMA
support and the DTS files are cleaned up.
The SDM630 platform DTS is at last merged and initial support for Sony
Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra is added.
* tag 'qcom-arm64-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (66 commits)
arm64: dts: qcom: pmi8998: Add nodes for LAB and IBB regulators
arm64: dts: sc7180: Add DSI and MDP OPP tables and power-domains
arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains
arm64: dts: qcom: sc7180: Move the fixed-perm property to SoC dtsi
arm64: dts: qcom: msm8916-samsung-a2015: Add accelerometer/magnetometer
arm64: dts: qcom: msm8916: Use higher I2C drive-strength only on DB410c
arm64: dts: qcom: msm8916: Simplify pinctrl configuration
arm64: dts: msm8916-samsung/longcheer: Move pinctrl/regulators to end of file
arm64: dts: qcom: sm8250: Drop tcsr_mutex syscon
arm64: dts: qcom: sc7180: Add missing properties for Wifi node
arm64: dts: qcom: Fix WiFi supplies on sc7180-idp
arm64: dts: sdm845: add Inline Crypto Engine registers and clock
arm64: dts: sc7180: Add sdhc opps and power-domains
arm64: dts: sdm845: Add sdhc opps and power-domains
arm64: dts: sc7180: Add OPP table for all qup devices
arm64: dts: sdm845: Add OPP table for all qup devices
arm64: dts: sc7180: Add qspi opps and power-domains
arm64: dts: sdm845: Add qspi opps and power-domains
arm64: dts: qcom: sdm845: Add cpu OPP tables
arm64: dts: qcom: sc7180: Drop the unused non-MSA SID
...
Link: https://lore.kernel.org/r/20200721044934.3430084-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Refactor hi6220-hikey dts to use phandles for overriding nodes
- Align UART node name to fix dtschema validator warnings for hi6220
- Add basic usb gadget support on hikey960
- Update adv7533 nodes to meet with the binding for hikey and hikey960
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Merge tag 'hisi-arm64-dt-for-5.9' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for 5.9
- Refactor hi6220-hikey dts to use phandles for overriding nodes
- Align UART node name to fix dtschema validator warnings for hi6220
- Add basic usb gadget support on hikey960
- Update adv7533 nodes to meet with the binding for hikey and hikey960
* tag 'hisi-arm64-dt-for-5.9' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisilicon: hikey: fixes to comply with adi, adv7533 DT binding
dts: hi3660: Add support for basic usb gadget on Hikey960
arm64: dts: hisilicon: Align UART nodename with dtschema
arm64: dts: hisilicon: Use phandles for overriding nodes in hi6220
Link: https://lore.kernel.org/r/5F165E8E.3030503@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
support, including:
- CPUFreq / Thermal throttling support for the H5
- Touchscreen support for the Pinephone
- New boards: PinePhone v1.2
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Merge tag 'sunxi-dt-for-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual number of patches to improve the Allwinner Device Tree
support, including:
- CPUFreq / Thermal throttling support for the H5
- Touchscreen support for the Pinephone
- New boards: PinePhone v1.2
* tag 'sunxi-dt-for-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h5: bananapi-m2-plus-v1.2: Tie in CPU OPPs
arm64: dts: allwinner: h5: libretech-all-h3-cc: Tie in CPU OPPs
arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones
arm64: dts: allwinner: h5: Add clock to CPU cores
ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
ARM: dts: sunxi: bananapi-m2-plus-v1.2: Add regulator supply to all CPU cores
ARM: dts: sunxi: libretech-all-h3-cc: Add regulator supply to all CPU cores
arm64: dts: sun50i-pinephone: dldo4 must not be >= 1.8V
arm64: dts: allwinner: Add support for PinePhone revision 1.2
dt-bindings: arm: sunxi: Add PinePhone 1.2 bindings
arm64: dts: sun50i-a64-pinephone: Add touchscreen support
arm64: dts: sun50i-a64-pinephone: Enable LCD support on PinePhone
ARM: dts: orange-pi-zero-plus2: add leds configuration
ARM: dts: orange-pi-zero-plus2: enable USB OTG port
Link: https://lore.kernel.org/r/fa48ffcb-3404-41bb-b065-a16717cf5688.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Update i.MX8M OCOTP device node name to match .yaml schema.
- Add ftm_alarm0 device support for layerscape SoCs.
- Add DSPI controller support for lx2160a device.
- A series from Peng Fan to add aliases for various devices on i.MX8
SoCs.
- Add Hantro G1/G2 VPU device support for imx8mq.
- Add more thermal zone support for ls1028a, ls1043a and ls1046a.
- Other small random changes.
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Merge tag 'imx-dt64-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree update for 5.9:
- Update i.MX8M OCOTP device node name to match .yaml schema.
- Add ftm_alarm0 device support for layerscape SoCs.
- Add DSPI controller support for lx2160a device.
- A series from Peng Fan to add aliases for various devices on i.MX8
SoCs.
- Add Hantro G1/G2 VPU device support for imx8mq.
- Add more thermal zone support for ls1028a, ls1043a and ls1046a.
- Other small random changes.
* tag 'imx-dt64-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (26 commits)
arm64: dts: lx2160a-rdb: fix shunt-resistor value
arm64: dts: ls1028a-qds: Add DSPI flash nodes
arm64: dts: lx2160a: Increase configuration space size
arm64: dts: zii-ultra: update MDIO speed and preamble
arm64: dts: ls1043a: update USB nodes status to match board config
arm64: dts: imx8mn-evk: add pca9450 for i.mx8mn-evk board
arm64: dts: imx8mp: add ddr pmu device node
arm64: dts: ls1043a: add more thermal zone support
arm64: dts: ls1046a: add more thermal zone support
arm64: dts: layerscape: add ftm_alarm0 node
arm64: dts: ls1028a: Add ftm_alarm0 DT node
arm64: dts: lx2160a: add ftm_alarm0 DT node
arm64: dts: lx2160a: add DT node for all DSPI controller
arm64: dts: lx2160a: add dspi controller DT nodes
arm64: dts: imx8mp: Add fallback compatible to ocotp node
arm64: dts: imx8qxp: Add ethernet alias
arm64: dts: imx8qxp: add i2c aliases
arm64: dts: imx8qxp: add alias for lsio MU
arm64: dts: imx8m: add mu node
arm64: dts: imx8m: change ocotp node name on i.MX8M SoCs
...
Link: https://lore.kernel.org/r/20200720085536.24138-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
were failing on older SoCs and one to fix Cedrus on the H6.
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Merge tag 'sunxi-fixes-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
Two fixes for the Allwinner SoCs, one to relax the CMA allocation ranges that
were failing on older SoCs and one to fix Cedrus on the H6.
* tag 'sunxi-fixes-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h6: Fix Cedrus IOMMU usage
ARM: dts sunxi: Relax a bit the CMA pool allocation range
Link: https://lore.kernel.org/r/e24f0608-6a4f-4163-b99e-a5f48e796184.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable PCA9450 regulator driver in arm64 defconfig.
- Enable RV8803 RTC and FSL_SAI audio support in arm64 defconfig to make
it useful for Kontron sl28 boards.
- Enable i.MX8MM clock and pinctrl driver in imx_v6_v7_defconfig to get
AARCH32 mode kernel work on AARCH64 hardware.
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Merge tag 'imx-defconfig-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig
i.MX defconfig update for 5.9:
- Enable PCA9450 regulator driver in arm64 defconfig.
- Enable RV8803 RTC and FSL_SAI audio support in arm64 defconfig to make
it useful for Kontron sl28 boards.
- Enable i.MX8MM clock and pinctrl driver in imx_v6_v7_defconfig to get
AARCH32 mode kernel work on AARCH64 hardware.
* tag 'imx-defconfig-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx_v6_v7_defconfig: Support i.MX8MM
arm64: defconfig: enable RTC and audio support on Kontron sl28 boards
arm64: defconfig: add pca9450 pmic driver
Link: https://lore.kernel.org/r/20200720085536.24138-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds support to enable HDMI out for
N10 and N8 combinations SBCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200720110230.367985-2-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0
ports.
This patch adds support to enable all these USB ports for
N10 and N8 combinations SBCs.
Note that the USB 3.0 port on RockPI N8 combination works
as USB 2.0 OTG since it is driven from RK3288.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200720110230.367985-1-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Activity Monitor Event Type Registers are named as AMEVTYPER{0,1}<n>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20200721091259.102756-1-vladimir.murzin@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This option now correctly depends on CPU_FREQ_THERMAL, so select it on the
architectures that implement the required functions,
arch_set_thermal_pressure() and arch_get_thermal_pressure().
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lkml.kernel.org/r/20200712165917.9168-4-valentin.schneider@arm.com
The following commit:
14533a16c4 ("thermal/cpu-cooling, sched/core: Move the arch_set_thermal_pressure() API to generic scheduler code")
moved the definition of arch_set_thermal_pressure() to sched/core.c, but
kept its declaration in linux/arch_topology.h. When building e.g. an x86
kernel with CONFIG_SCHED_THERMAL_PRESSURE=y, cpufreq_cooling.c ends up
getting the declaration of arch_set_thermal_pressure() from
include/linux/arch_topology.h, which is somewhat awkward.
On top of this, sched/core.c unconditionally defines
o The thermal_pressure percpu variable
o arch_set_thermal_pressure()
while arch_scale_thermal_pressure() does nothing unless redefined by the
architecture.
arch_*() functions are meant to be defined by architectures, so revert the
aforementioned commit and re-implement it in a way that keeps
arch_set_thermal_pressure() architecture-definable, and doesn't define the
thermal pressure percpu variable for kernels that don't need
it (CONFIG_SCHED_THERMAL_PRESSURE=n).
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200712165917.9168-2-valentin.schneider@arm.com
Adding maximum speed property for DWC3 USB node which can be used
for setting interconnect bandwidth.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1595317489-18432-3-git-send-email-sanm@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add "arm,coresight-loses-context-with-cpu" property to coresight
ETM nodes to avoid failure of trace session because of losing
context on entering deep idle states.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200721071343.2898-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the OPP table for the Mali Bifrost GPU and drop the hardcoded
initial clock configuration. This enables GPU DVFS and thus saves power
when the GPU is not in use while still being able switch to a higher
clock on demand.
Set the GP0_PLL clock to 744MHz (which is the only frequency which
cannot be derived from the FCLK dividers) as the clock driver avoids
setting the parent clock rates so the HIFI PLL clock isn't changed (as
that's reserved for audio).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200719173213.639540-4-martin.blumenstingl@googlemail.com
Add the OPP table for the Mali-T820 GPU and drop the hardcoded initial
clock configuration. This enables GPU DVFS and thus saves power when the
GPU is not in use while still being able switch to a higher clock on
demand.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200719173213.639540-3-martin.blumenstingl@googlemail.com
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial
clock configuration. This enables GPU DVFS and thus saves power when the
GPU is not in use while still being able switch to a higher clock on
demand.
Set the GP0_PLL clock to 744MHz (which is the only frequency which
cannot be derived from the FCLK dividers) as the clock driver avoids
setting the parent clock rates so the MPLL clocks aren't changed (as
these are reserved for audio). The only exception to this is the GXL
S805X package because the 744MHz OPP isn't working correctly there.
While here, make most of meson-gxl-mali re-usable to reduce the amount
of duplicate code between GXBB and GXL. This is more important now as we
don't want to duplicate the GPU OPP table.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200719173213.639540-2-martin.blumenstingl@googlemail.com
The WeTek Core2 is a commercial device based on the Amlogic Q200 reference
design but with the following differences:
- 3GB RAM, 32GB eMMC
- Blue and Red LEDs used to signal on/off status
- uart_AO can be accessed after opening the case; soldering required
- USB OTG is not accessible (inside the case)
- Realtek RTL8152 Ethernet (internal USB connection)
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200719021421.7959-3-christianshewitt@gmail.com
Add initial audio support limited to HDMI i2s, copying the config
from the existing VIM3 device-tree.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200718072532.8427-3-christianshewitt@gmail.com
Some new PMU events can been detected by PMCEID1_EL0, but it can't
be listed, Let's expose these through sysfs.
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/1595328573-12751-2-git-send-email-zhangshaokun@hisilicon.com
Signed-off-by: Will Deacon <will@kernel.org>
Although vmlinux.lds.S smells like an assembly file and is compiled
with __ASSEMBLY__ defined, it's actually just fed to the preprocessor to
create our linker script. This means that any assembly macros defined
by headers that it includes will result in a helpful link error:
| aarch64-linux-gnu-ld:./arch/arm64/kernel/vmlinux.lds:1: syntax error
In preparation for an arm64-private asm/rwonce.h implementation, which
will end up pulling assembly macros into linux/compiler.h, reduce the
number of headers we include directly and transitively in vmlinux.lds.S
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will@kernel.org>
Now that 'smp_read_barrier_depends()' has gone the way of the Norwegian
Blue, drop the inclusion of <asm/barrier.h> in 'asm-generic/rwonce.h'.
This requires fixups to some architecture vdso headers which were
previously relying on 'asm/barrier.h' coming in via 'linux/compiler.h'.
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will@kernel.org>
The VIM3/VIM3L Boards use w25q128 not w25q32 - this is a cosmetic change
only - the device probes fine with the current device-tree.
Fixes: 0e1610e726 ("arm64: dts: khadas-vim3: add SPIFC controller node")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200718054505.4165-1-christianshewitt@gmail.com
The Bananapi M2 Plus H5 v1.2 can work with the standard H5 OPPs.
Tie them in to enable CPU frequency scaling.
The original Bananapi M2 Plus H5 is left out for now, as adding
the fixed regulator along with the enable pin seemed to cause some
glitching in Linux.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-9-wens@kernel.org
The Libre Computer ALL-H3-CC H5 variant can work with the standard H5
OPPs. Tie them in to enable CPU frequency scaling.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-8-wens@kernel.org
Add an OPP (Operating Performance Points) table for the CPU cores for
boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the
H5. The table originates from Armbian, but the maximum voltage is raised
slightly to account for boards using slightly higher voltages.
The table and tie in to the CPU cores are put in a separate dtsi file
that board files can include to opt in. Or they can define their own
tables if the standard one does not fit.
This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi
M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V
regulator, while the latter has a GPIO controlled regulator switchable
between 1.1V and 1.3V.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-7-wens@kernel.org
This enables passive cooling by down-regulating CPU voltage and frequency.
The trip points were copied from the H3.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-6-wens@kernel.org
The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200717160053.31191-5-wens@kernel.org
This completes the ARM64 cap_user_time support.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Link: https://lore.kernel.org/r/20200716051130.4359-7-leo.yan@linaro.org
Signed-off-by: Will Deacon <will@kernel.org>
When sched_clock is running on anything other than arch_timer, don't
advertise cap_user_time*.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Link: https://lore.kernel.org/r/20200716051130.4359-5-leo.yan@linaro.org
Requested-by: Will Deacon <will@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
As reported by Leo; the existing implementation is broken when the
clock and counter don't intersect at 0.
Use the sched_clock's struct clock_read_data information to correctly
implement cap_user_time and cap_user_time_zero.
Note that the ARM64 counter is architecturally only guaranteed to be
56bit wide (implementations are allowed to be wider) and the existing
perf ABI cannot deal with wrap-around.
This implementation should also be faster than the old; seeing how we
don't need to recompute mult and shift all the time.
[leoyan: Use mul_u64_u32_shr() to convert cyc to ns to avoid overflow]
Reported-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Link: https://lore.kernel.org/r/20200716051130.4359-4-leo.yan@linaro.org
Signed-off-by: Will Deacon <will@kernel.org>
When PMU event ID is equal or greater than 0x4000, it will be reduced
by 0x4000 and it is not the raw number in the sysfs. Let's correct it
and obtain the raw event ID.
Before this patch:
cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
event=0x001
After this patch:
cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
event=0x4001
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/1592487344-30555-3-git-send-email-zhangshaokun@hisilicon.com
[will: fixed formatting of 'if' condition]
Signed-off-by: Will Deacon <will@kernel.org>
Fix value of shunt-resistor property.
The LX2160A-RDB has 500 uOhm shunt for
the INA220, not 1000 uOhm. Unless
it will get wrong power consumption(1/2)
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Now that the ->compat_{get,set}sockopt proto_ops methods are gone
there is no good reason left to keep the compat syscalls separate.
This fixes the odd use of unsigned int for the compat_setsockopt
optlen and the missing sock_use_custom_sol_socket.
It would also easily allow running the eBPF hooks for the compat
syscalls, but such a large change in behavior does not belong into
a consolidation patch like this one.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
The commit below caused a regression for clearfog-gt-8k, where the link
between the switch and the host does not come up.
Investigation revealed two issues:
- MV88E6xxx DSA no longer allows an in-band link to come up as the link
is programmed to be forced down. Commit "net: dsa: mv88e6xxx: fix
in-band AN link establishment" addresses this.
- The dts configured dissimilar link modes at each end of the host to
switch link; the host was configured using a fixed link (so has no
in-band status) and the switch was configured to expect in-band
status.
With both issues fixed, the regression is resolved.
Fixes: 34b5e6a33c ("net: dsa: mv88e6xxx: Configure MAC when using fixed link")
Reported-by: Martin Rowe <martin.p.rowe@gmail.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Some of gmac, sdmmc node properties are common across rk3288 and
rk3399pro SOM's so move them into Carrier dtsi.
Chosen node is specific to rk3399pro configure SBC, so move it into
RockPI N10 dts.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-5-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Supply regulators are common across different variants of vmarc SOM's
since the Type C power controller IC is part of the carrier board.
So, move the supply regulators into carrier board dtsi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-4-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
I2C nodes and associated slave devices defined in Carrier board
are specific to rk3399pro vmrac SOM.
So, move them into SOM dtsi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-2-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
'bus-width' has been added to px30.dtsi mmc nodes, so now it can be
removed from the dts files that include it.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200715070954.1992-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This time there are a number of actual code fixes, plus
a small set of device tree issues getting addressed:
- Renesas:
- one defconfig cleanup to allow a later Kconfig change
- Intel socfpga:
- enable QSPI devices on some machines
- fix DTC validation warnings
- TI OMAP:
- Two DEBUG_ATOMIC_SLEEP fixes for ti-sysc interconnect target module
driver
- A regression fix for ti-sysc no-idle handling that caused issues
compared to earlier platform data based booting
- A fix for memory leak for omap_hwmod_allocate_module
- Fix d_can driver probe for am437x
- NXP i.MX
- A couple of fixes on i.MX platform device registration code to stop
the use of invalid IRQ 0.
- Fix a regression seen on ls1021a platform, caused by commit
52102a3ba6 ("soc: imx: move cpu code to drivers/soc/imx").
- Fix a misconfiguration of audio SSI on imx6qdl-gw551x board.
- Amlogic Meson
- misc DT fixes
- SoC ID fixes to detect all chips correctly
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-fixes-5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc into master
Pull ARM SoC fixes from Arnd Bergmann:
"This time there are a number of actual code fixes, plus a small set of
device tree issues getting addressed:
Renesas:
- one defconfig cleanup to allow a later Kconfig change
Intel socfpga:
- enable QSPI devices on some machines
- fix DTC validation warnings
TI OMAP:
- Two DEBUG_ATOMIC_SLEEP fixes for ti-sysc interconnect target
module driver
- A regression fix for ti-sysc no-idle handling that caused issues
compared to earlier platform data based booting
- A fix for memory leak for omap_hwmod_allocate_module
- Fix d_can driver probe for am437x
NXP i.MX:
- A couple of fixes on i.MX platform device registration code to
stop the use of invalid IRQ 0.
- Fix a regression seen on ls1021a platform, caused by commit
52102a3ba6 ("soc: imx: move cpu code to drivers/soc/imx").
- Fix a misconfiguration of audio SSI on imx6qdl-gw551x board.
Amlogic Meson:
- misc DT fixes
- SoC ID fixes to detect all chips correctly"
* tag 'arm-fixes-5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema
ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
arm64: dts: stratix10: increase QSPI reg address in nand dts file
arm64: dts: stratix10: add status to qspi dts node
arm64: dts: agilex: add status to qspi dts node
ARM: dts: Fix dcan driver probe failed on am437x platform
ARM: OMAP2+: Fix possible memory leak in omap_hwmod_allocate_module
arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
soc: imx: check ls1021a
ARM: imx: Remove imx_add_imx_dma() unused irq_err argument
ARM: imx: Provide correct number of resources when registering gpio devices
ARM: dts: imx6qdl-gw551x: fix audio SSI
bus: ti-sysc: Do not disable on suspend for no-idle
bus: ti-sysc: Fix sleeping function called from invalid context for RTC quirk
bus: ti-sysc: Fix wakeirq sleeping function called from invalid context
ARM: dts: meson: Align L2 cache-controller nodename with dtschema
arm64: dts: meson-gxl-s805x: reduce initial Mali450 core frequency
arm64: dts: meson: add missing gxl rng clock
soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's
- Fix kernel text addresses for relocatable images booting using EFI
and with KASLR disabled so that they match the vmlinux ELF binary.
- Fix unloading and unbinding of PMU driver modules.
- Fix generic mmiowb() when writeX() is called from preemptible context
(reported by the riscv folks).
- Fix ptrace hardware single-step interactions with signal handlers,
system calls and reverse debugging.
- Fix reporting of 64-bit x0 register for 32-bit tasks via 'perf_regs'.
- Add comments describing syscall entry/exit tracing ABI.
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux into master
Pull arm64 fixes from Will Deacon:
"A batch of arm64 fixes.
Although the diffstat is a bit larger than we'd usually have at this
stage, a decent amount of it is the addition of comments describing
our syscall tracing behaviour, and also a sweep across all the modular
arm64 PMU drivers to make them rebust against unloading and unbinding.
There are a couple of minor things kicking around at the moment (CPU
errata and module PLTs for very large modules), but I'm not expecting
any significant changes now for us in 5.8.
- Fix kernel text addresses for relocatable images booting using EFI
and with KASLR disabled so that they match the vmlinux ELF binary.
- Fix unloading and unbinding of PMU driver modules.
- Fix generic mmiowb() when writeX() is called from preemptible
context (reported by the riscv folks).
- Fix ptrace hardware single-step interactions with signal handlers,
system calls and reverse debugging.
- Fix reporting of 64-bit x0 register for 32-bit tasks via
'perf_regs'.
- Add comments describing syscall entry/exit tracing ABI"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
drivers/perf: Prevent forced unbinding of PMU drivers
asm-generic/mmiowb: Allow mmiowb_set_pending() when preemptible()
arm64: Use test_tsk_thread_flag() for checking TIF_SINGLESTEP
arm64: ptrace: Use NO_SYSCALL instead of -1 in syscall_trace_enter()
arm64: syscall: Expand the comment about ptrace and syscall(-1)
arm64: ptrace: Add a comment describing our syscall entry/exit trap ABI
arm64: compat: Ensure upper 32 bits of x0 are zero on syscall return
arm64: ptrace: Override SPSR.SS when single-stepping is enabled
arm64: ptrace: Consistently use pseudo-singlestep exceptions
drivers/perf: Fix kernel panic when rmmod PMU modules during perf sampling
efi/libstub/arm64: Retain 2MB kernel Image alignment if !KASLR
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1594292674-15632-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1594292674-15632-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This contains a slew of fixes in preparation for validating device trees
against json-schema bindings. In addition, this enables the CPU complex
(for CPU frequency scaling) and GPU on Tegra194.
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Merge tag 'tegra-for-5.9-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.9-rc1
This contains a slew of fixes in preparation for validating device trees
against json-schema bindings. In addition, this enables the CPU complex
(for CPU frequency scaling) and GPU on Tegra194.
* tag 'tegra-for-5.9-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (56 commits)
arm64: tegra: Add the GPU on Tegra194
arm64: tegra: Add compatible string for Tegra194 CPU complex
arm64: tegra: Add HDMI supplies on Norrin
arm64: tegra: Add #{address,size}-cells for VI I2C on Tegra210
arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C
arm64: tegra: Add clocks and resets for ISP on Tegra210
arm64: tegra: Fix compatible string for DPAUX on Tegra210
arm64: tegra: Add i2c-bus subnode for DPAUX controllers
arm64: tegra: Sort aliases alphabetically
arm64: tegra: Remove spurious tabs
arm64: tegra: Populate VBUS for USB3 on Jetson TX2
arm64: tegra: Enable DFLL support on Jetson Nano
arm64: tegra: Add support for Jetson Xavier NX
arm64: tegra: Re-order PCIe aperture mappings
arm64: tegra: Enable Tegra VI CSI support for Jetson Nano
arm64: tegra: jetson-tx1: Add camera supplies
arm64: tegra: Fix order of XUSB controller clocks
arm64: tegra: Rename cbb@0 to bus@0 on Tegra194
arm64: tegra: Sort nodes by unit-address on Jetson Nano
arm64: tegra: Various fixes for PMICs
...
Link: https://lore.kernel.org/r/20200717161300.1661002-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Replace CONFIG_PCIE_RCAR by CONFIG_PCIE_RCAR_HOST in the defconfig,
to unblock a planned Kconfig change.
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Merge tag 'renesas-fixes-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v5.8
- Replace CONFIG_PCIE_RCAR by CONFIG_PCIE_RCAR_HOST in the defconfig,
to unblock a planned Kconfig change.
* tag 'renesas-fixes-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
Link: https://lore.kernel.org/r/20200717100523.15418-1-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.
Link: https://lore.kernel.org/r/20200717090414.313530-6-daniele.alessandrelli@linux.intel.com
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable CONFIG_SDHCI_AM654 to Support AM65x sdhci controller.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Select TI chip id driver for TI's SoCs based on K3 architecture to provide
this information to user space and Kernel as it is required by other
drivers to determine SoC revision to function properly.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774e1 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-14-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the device nodes for RZ/G2H SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds the CMT[0123] device tree nodes to the
r8a774e1 SoC specific DT.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add thermal support for R8A774E1 (RZ/G2H) SoC.
Based on the work done for r8a774a1 SoC.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The RZ/G2H (r8a774e1) comes with two clusters of processors, similarly to
the r8a774a1. The first cluster is made of A57s, the second cluster is made
of A53s.
The operating points for the cluster with the A57s are:
Frequency | Voltage
----------|---------
500 MHz | 0.82V
1.0 GHz | 0.82V
1.5 GHz | 0.82V
The operating points for the cluster with the A53s are:
Frequency | Voltage
----------|---------
800 MHz | 0.82V
1.0 GHz | 0.82V
1.2 GHz | 0.82V
This patch adds the definitions for the operating points to the SoC
specific DT.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Beacon EmebeddedWorks, formerly Logic PD is introducing a new
SOM and development kit based on the RZ/G2M SoC from Renesas.
The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1
cellular radio.
The Baseboard has Ethernet, USB, HDMI, stereo audio in and out,
along with a variety of push buttons and LED's, and support for
a parallel RGB and an LVDS display.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200715140622.1295370-1-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board.
These boards are identical with the ones for RZ/G2M[N].
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594230511-24790-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT)
to debounce the CC lines in order to detect attach and plug orientation
and reflect the correct DIR status. [1]
On the EVM however we need to wait upto 700ms before sampling the
Type-C DIR line else we can get incorrect direction state.
[1] http://www.ti.com/lit/ds/symlink/tusb321.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
USB0 supports super-speed mode on the EVM. Enable that.
On the EVM, USB0 uses SERDES3 for super-speed lane.
Since USB0 is a type-C port, it needs to support lane swapping
for cable flip support. This is provided using SERDES lane
swap feature. Provide the Type-C cable orientation GPIO
to the SERDES Wrapper driver.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The USB controllers can be connected to one of the 2 SERDESes
using a MUX. Add a MUX controller node fot that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add DT nodes for all instances of WIZ and SERDES modules.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The preferable name for gic-its is msi-controller, so rename it to fix
dtbs_check warning:
k3-j721e-common-proc-board.dt.yaml: interrupt-controller@1800000:
gic-its@1820000: False schema does not allow {'compatible':
['arm,gic-v3-its'], 'reg': [[0, 25296896, 0, 65536]],
'socionext,synquacer-pre-its': [[16777216, 4194304]], 'msi-controller':
True, '#msi-cells': [[1]]}
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Rename smmu node to iommu to fix dtbs_check warning:
k3-j721e-common-proc-board.dt.yaml: smmu@36600000: $nodename:0: 'smmu@36600000' does not match '^iommu@[0-9a-f]*'
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
With silicon revision 2.0, add support for SD card on the am65x-evm.
Boards with silicon revision 1.0 are susceptible to interface issues
because of erratas i2025 and i2026[1] and are recommended to disable
this node.
[1] Am654x Silicon Revision 1.0 errata: https://www.ti.com/lit/pdf/sprz452
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add support for the 2nd SDHCI controller on TI's AM654x SoCs.
Although it supports upto SDR104 (100 MBps @ 200 MHz) speed mode,
only enable support upto High Speed (25 MBps @ 50 MHz) for now.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The codec is wired in multi DIN/DOUT setup (DIN1/2/3/4/DOUT1/2/3 is
connected to McASP serializer).
To support wide range of audio features a generic sound card can not be
used since we need to use different reference clock source for 44.1 and
48 KHz family of sampling rates.
Depending on the sample size we also need to use different slot width to
be able to support 16 and 24 bits.
There are couple of notable difference compared to DIN1/DOUT1 mode:
the channel mapping is 'random' for first look compared to the single
serializer setup:
_ _ _
|o|c1 |o|p1 |o|p3
_ | | | | | |
|o|c3 |o|c2 |o|p4 |o|p2
------------------------
c1/2/3 - capture jacks (3rd is line)
p1/2/3/4 - playback jacks (4th is line)
2 channel audio (stereo):
0 (left): p1/c1 left
1 (right): p1/c1 right
4 channel audio:
0: p1/c1 left
1: p2/c2 left
2: p1/c1 right
3: p2/c2 right
6 channel audio
0: p1/c1 left
1: p2/c2 left
2: p3/c3 left
3: p1/c1 right
4: p2/c2 right
5: p3/c3 right
8 channel audio
0: p1/c1 left
1: p2/c2 left
2: p3/c3 left
3: p4 left
4: p1/c1 right
5: p2/c2 right
6: p3/c3 right
7: p4 right
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Two pimux entry is present with the same name, remove one of them.
Fixes: cb27354b38 ("arm64: dts: ti: k3-j721e: Add DT nodes for few peripherials")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
We refactored the CrOS EC drivers moving part of the code from the MFD
subsystem to the platform chrome subsystem. During this change we needed
to rename some config options, so, update the defconfigs accordingly.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hi3660-hikey960.dts:
Define a 'ports' node for 'adv7533: adv7533@39' and the
'adi,dsi-lanes' property to make it compliant with the adi,adv7533 DT
binding.
This fills the requirements to meet the binding requirements,
remote endpoints are not defined.
hi6220-hikey.dts:
Change property name s/pd-gpio/pd-gpios, gpio properties should be
plural. This is just a cosmetic change.
Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch adds basic core dwc3, usb phy and rt1711h nodes for
usb support on Hikey960.
This does not enable the mux/hub functionality on the board, so
the USB-A host ports will not function, but does allow the USB-C
port to function in gadget mode (unfortunately not in host, as
the hub/mux functionality is needed to enable vbus output to
power devices in host mode).
This is based on an old patch originally by Yu Chen.
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: YongQin Liu <yongqin.liu@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Fix dtschema validator warnings like:
uart@f8015000: $nodename:0: 'uart@f8015000' does not match '^serial(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
When overriding nodes, usage of phandles instead of full paths reduces
possible mistakes (e.g. in duplicated unit address) and removes
duplicate data. The UART nodes were extended via full path and phandle
which makes it difficult to review and spot actual differences.
No functional change (no difference in dtx_diff).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
All the platforms using SC7180 SoC are expected to have the wlan firmware
memory statically mapped by the Trusted Firmware. Hence move back the
qcom,msa-fixed-perm property to the SoC dtsi.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Fixes: 7d48456608 ("arm64: dts: qcom: sc7180: Add missing properties for Wifi node")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200716191746.23196-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
On Tegra194, data on valid operating points for the CPUs needs to be
queried from BPMP. However, there is no node representing CPU complex.
So, add a compatible string to the 'cpus' node instead of using dummy
node to bind the cpufreq driver to. Also, add reference to the BPMP
instance for the CPU complex.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR controller needs the AVDD I/O and VDD HDMI PLL supplies in order
to operate correctly. Make sure to specify them for the Norrin board.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The VI I2C controller provides an I2C bus and therefore needs to define
the #address-cells and #size-cells properties.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 VI I2C is in VE power domain and i2c-vi node should have
power-domains property.
Current Tegra210 i2c-vi device node is missing both VI I2C clocks
and power-domains property.
This patch adds them.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Rather than open-code test_tsk_thread_flag() at each callsite, simply
replace the couple of offenders with calls to test_tsk_thread_flag()
directly.
Signed-off-by: Will Deacon <will@kernel.org>
Setting a system call number of -1 is special, as it indicates that the
current system call should be skipped.
Use NO_SYSCALL instead of -1 when checking for this scenario, which is
different from the -1 returned due to a seccomp failure.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Keno Fischer <keno@juliacomputing.com>
Cc: Luis Machado <luis.machado@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
If a task executes syscall(-1), we intercept this early and force x0 to
be -ENOSYS so that we don't need to distinguish this scenario from one
where the scno is -1 because a tracer wants to skip the system call
using ptrace. With the return value set, the return path is the same as
the skip case.
Although there is a one-line comment noting this in el0_svc_common(), it
misses out most of the detail. Expand the comment to describe a bit more
about what is going on.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Keno Fischer <keno@juliacomputing.com>
Cc: Luis Machado <luis.machado@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
Our tracehook logic for syscall entry/exit raises a SIGTRAP back to the
tracer following a ptrace request such as PTRACE_SYSCALL. As part of this
procedure, we clobber the reported value of one of the tracee's general
purpose registers (x7 for native tasks, r12 for compat) to indicate
whether the stop occurred on syscall entry or exit. This is a slightly
unfortunate ABI, as it prevents the tracer from accessing the real
register value and is at odds with other similar stops such as seccomp
traps.
Since we're stuck with this ABI, expand the comment in our tracehook
logic to acknowledge the issue and describe the behaviour in more detail.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Luis Machado <luis.machado@linaro.org>
Reported-by: Keno Fischer <keno@juliacomputing.com>
Signed-off-by: Will Deacon <will@kernel.org>
Although we zero the upper bits of x0 on entry to the kernel from an
AArch32 task, we do not clear them on the exception return path and can
therefore expose 64-bit sign extended syscall return values to userspace
via interfaces such as the 'perf_regs' ABI, which deal exclusively with
64-bit registers.
Explicitly clear the upper 32 bits of x0 on return from a compat system
call.
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Keno Fischer <keno@juliacomputing.com>
Cc: Luis Machado <luis.machado@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
Luis reports that, when reverse debugging with GDB, single-step does not
function as expected on arm64:
| I've noticed, under very specific conditions, that a PTRACE_SINGLESTEP
| request by GDB won't execute the underlying instruction. As a consequence,
| the PC doesn't move, but we return a SIGTRAP just like we would for a
| regular successful PTRACE_SINGLESTEP request.
The underlying problem is that when the CPU register state is restored
as part of a reverse step, the SPSR.SS bit is cleared and so the hardware
single-step state can transition to the "active-pending" state, causing
an unexpected step exception to be taken immediately if a step operation
is attempted.
In hindsight, we probably shouldn't have exposed SPSR.SS in the pstate
accessible by the GPR regset, but it's a bit late for that now. Instead,
simply prevent userspace from configuring the bit to a value which is
inconsistent with the TIF_SINGLESTEP state for the task being traced.
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Keno Fischer <keno@juliacomputing.com>
Link: https://lore.kernel.org/r/1eed6d69-d53d-9657-1fc9-c089be07f98c@linaro.org
Reported-by: Luis Machado <luis.machado@linaro.org>
Tested-by: Luis Machado <luis.machado@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
Although the arm64 single-step state machine can be fast-forwarded in
cases where we wish to generate a SIGTRAP without actually executing an
instruction, this has two major limitations outside of simply skipping
an instruction due to emulation.
1. Stepping out of a ptrace signal stop into a signal handler where
SIGTRAP is blocked. Fast-forwarding the stepping state machine in
this case will result in a forced SIGTRAP, with the handler reset to
SIG_DFL.
2. The hardware implicitly fast-forwards the state machine when executing
an SVC instruction for issuing a system call. This can interact badly
with subsequent ptrace stops signalled during the execution of the
system call (e.g. SYSCALL_EXIT or seccomp traps), as they may corrupt
the stepping state by updating the PSTATE for the tracee.
Resolve both of these issues by injecting a pseudo-singlestep exception
on entry to a signal handler and also on return to userspace following a
system call.
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Tested-by: Luis Machado <luis.machado@linaro.org>
Reported-by: Keno Fischer <keno@juliacomputing.com>
Signed-off-by: Will Deacon <will@kernel.org>
Make the Makefile for building Renesas DTB files easier to read and
maintain:
- Get rid of line continuations,
- Use a single entry per line,
- Sort SoCs and boards alphabetically,
- Separate SoCs by blank lines.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200706154015.29257-1-geert+renesas@glider.be
The PHY mode already defaults to RGMII in the RZ/G2E base SoC DTS file,
so there is no need to specify the same value in board files.
Fixes: 6b170cd3ed ("arm64: dts: renesas: cat875: Add ethernet support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200706151400.23105-1-geert+renesas@glider.be
Now that the IOMMU driver has been introduced, it prevents any access from
a DMA master going through it that hasn't properly mapped the pages, and
that link is set up through the iommus property.
Unfortunately we forgot to add that property to the video engine node when
adding the IOMMU node, so now any DMA access is broken.
Fixes: b3a0a2f910 ("arm64: dts: allwinner: h6: Add IOMMU")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200628180804.79026-1-maxime@cerno.tech
A3U/A5U both use a Bosch BMC150 accelerometer/magnetometer combo.
The chip provides two separate I2C devices for the accelerometer
and magnetometer that are already supported by the bmc150-accel
and bmc150-magn driver.
The only difference between A3U/A5U is the way the sensor is
mounted on the mainboard - set the mount-matrix in the
device-specific device tree part to handle that difference.
Co-developed-by: Michael Srba <michael.srba@seznam.cz>
Signed-off-by: Michael Srba <michael.srba@seznam.cz>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200622151751.408995-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Commit c240f29e75 ("arm64: dts: set the default i2c pin drive strength to 16mA")
changed the default drive-strength for I2C pins in msm8916-pins.dtsi
to the maximum possible (16 mA).
While this makes sense for apq8016-sbc (DB410c) where you can connect
an arbitrary amount of I2C devices with level shifters etc, there is
no need to use a higher drive strength for other MSM8916 devices.
The minimum drive strength (2 mA) seems to be totally sufficient
to have everything work there.
With the short pinctrl nodes introduced earlier we can easily override
the drive-strength only for apq8016-sbc now. Use that and change
the default back to 2 mA.
i2c1_default/i2c5_default are already using 2 mA because they were
added separately later and are not used in apq8016-sbc.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200622151751.408995-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
So far we have been separating pinctrl entries into pinmux/pinconf.
It turns out it is also possible to combine them: The advantage is
that the device tree is overall more concise because the "pins"
to configure just need to be specified once, not separately for
pinmux/pinconf.
Using the simpler form only for new entries would be rather confusing.
This commit makes all MSM8916 device trees use the simplfied form.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200622151751.408995-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
It is helpful to be able to see all hardware components in one part
of the device tree, without having to scroll over the large amount
of regulator/pinctrl nodes. Keep those separated at the end of the file
to make navigation a bit easier.
This also makes it consistent with the order used in apq8016-sbc.dtsi.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200622151751.408995-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Now that we don't need the intermediate syscon to represent the TCSR
mutexes, update the dts to describe the TCSR mutex directly under /soc.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200622075956.171058-5-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The wlan firmware memory is statically mapped in
the Trusted Firmware, hence the wlan driver does
not need to map/unmap this region dynamically.
Hence add the property to indicate the wlan driver
to not map/unamp the firmware memory region
dynamically.
Also add the chain1 voltage supply for wlan.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
Link: https://lore.kernel.org/r/1594615586-17055-1-git-send-email-pillair@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The WiFi supplies that were added recently can't have done anything
useful because they were missing the "-supply" suffix. Booting
without the "-supply" suffix would give these messages:
ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-0.8-cx-mx not found, using dummy regulator
ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.8-xo not found, using dummy regulator
ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.3-rfa not found, using dummy regulator
ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-3.3-ch0 not found, using dummy regulator
Let's add the "-supply" suffix.
Tested-by: Rakesh Pillai <pillair@codeaurora.org>
Reviewed-by: Rakesh Pillai <pillair@codeaurora.org>
Fixes: 1e7594a38f ("arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200625131658.REPOST.1.I32960cd32bb84d6db4127c906d7e371fa29caebf@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Match the QSPI reg address in the socfpga_stratix10_socdk.dts file.
Fixes: 80f132d737 ("arm64: dts: increase the QSPI reg address for Stratix10 and Agilex")
Cc: linux-stable <stable@vger.kernel.org> # >= v5.6
Signed-off-by: Dinh Nguyen <dinh.nguyen@intel.com>
Add __TLBI_VADDR_RANGE macro and rewrite __flush_tlb_range().
When cpu supports TLBI feature, the minimum range granularity is
decided by 'scale', so we can not flush all pages by one instruction
in some cases.
For example, when the pages = 0xe81a, let's start 'scale' from
maximum, and find right 'num' for each 'scale':
1. scale = 3, we can flush no pages because the minimum range is
2^(5*3 + 1) = 0x10000.
2. scale = 2, the minimum range is 2^(5*2 + 1) = 0x800, we can
flush 0xe800 pages this time, the num = 0xe800/0x800 - 1 = 0x1c.
Remaining pages is 0x1a;
3. scale = 1, the minimum range is 2^(5*1 + 1) = 0x40, no page
can be flushed.
4. scale = 0, we flush the remaining 0x1a pages, the num =
0x1a/0x2 - 1 = 0xd.
However, in most scenarios, the pages = 1 when flush_tlb_range() is
called. Start from scale = 3 or other proper value (such as scale =
ilog2(pages)), will incur extra overhead.
So increase 'scale' from 0 to maximum, the flush order is exactly
opposite to the example.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200715071945.897-4-yezhenyu2@huawei.com
[catalin.marinas@arm.com: removed unnecessary masks in __TLBI_VADDR_RANGE]
[catalin.marinas@arm.com: __TLB_RANGE_NUM subtracts 1]
[catalin.marinas@arm.com: minor adjustments to the comments]
[catalin.marinas@arm.com: introduce system_supports_tlb_range()]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
TLBI RANGE feature instoduces new assembly instructions and only
support by binutils >= 2.30. Add necessary Kconfig logic to allow
this to be enabled and pass '-march=armv8.4-a' to KBUILD_CFLAGS.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200715071945.897-3-yezhenyu2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
range of input addresses. This patch detect this feature.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200715071945.897-2-yezhenyu2@huawei.com
[catalin.marinas@arm.com: some renaming for consistency]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Currently 'hugetlb_cma=' command line argument does not create CMA area on
ARM64_16K_PAGES and ARM64_64K_PAGES based platforms. Instead, it just ends
up with the following warning message. Reason being, hugetlb_cma_reserve()
never gets called for these huge page sizes.
[ 64.255669] hugetlb_cma: the option isn't supported by current arch
This enables CMA areas reservation on ARM64_16K_PAGES and ARM64_64K_PAGES
configs by defining an unified arm64_hugetlb_cma_reseve() that is wrapped
in CONFIG_CMA. Call site for arm64_hugetlb_cma_reserve() is also protected
as <asm/hugetlb.h> is conditionally included and hence cannot contain stub
for the inverse config i.e !(CONFIG_HUGETLB_PAGE && CONFIG_CMA).
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Kravetz <mike.kravetz@oracle.com>
Cc: Barry Song <song.bao.hua@hisilicon.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/1593578521-24672-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The Tegra210 DPAUX controller is not compatible with that found on
Tegra124, so it must have a separate compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DPAUX controller device tree bindings require the bus to have an
i2c-bus subnode to distinguish between I2C clients and pinmux groups.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The VBUS for USB3 connector on the Jetson TX2 is connected to the
vdd_usb1 supply and although this is populated for the USB2 port
on the USB3 connector it is not populated for the USB3 port and
causes the following warning to be seen on boot ...
usb3-0: supply vbus not found, using dummy regulator
Fix this by also adding the VBUS supply to the USB3 port.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Populate the DFLL node and corresponding PWM pin nodes in order to
enable CPUFREQ support on the Jetson Nano platform.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the device-tree source files for the Tegra194 Jetson Xavier NX
Developer Kit. The Xavier NX Developer Kit consists of a small form
factor system-on-module (SOM) board (part number p3668-0000) and a
carrier board (part number p3509-0000).
The Xavier NX Developer Kit SOM features a micro-SD card slot, however,
there is also a variant of the SOM available that features a 16GB eMMC.
Given that the carrier board can be used with the different SOM
variants, that have different part numbers, both the compatible string
and file name of the device-tree source file for the Developer Kit is a
concatenation of the SOM and carrier board part numbers.
Based on some initial work by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Re-order Tegra194's PCIe aperture mappings to have IO window moved to
64-bit aperture and have the entire 32-bit aperture used for accessing
the configuration space. This makes it to use the entire 32MB of the 32-bit
aperture for ECAM purpose while booting through ACPI.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch enables VI and CSI in device tree for Jetson Nano.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jetson TX1 development board has a camera expansion connector which
has 2V8, 1V8 and 1V2 supplies to power up the camera sensor on the
supported camera modules.
Camera module designed as per Jetson TX1 camera expansion connector
may use these supplies for camera sensor avdd 2V8, digital core 1V8,
and digital interface 1V2 voltages.
These supplies are from fixed regulators on TX1 carrier board with
enable control signals from I2C GPIO expanders.
This patch adds these camera supplies to Jetson TX1 device tree to
allow using these when a camera module is used.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This is purely to make the json-schema validation tools happy because
they cannot deal with string arrays that may be in arbitrary order.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The control backbone is a simple-bus and hence its device tree node
should be named "bus@<unit-address>" according to the bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Standardize on "pmic" as the node name for the PMIC on Tegra210 systems
and use consistent names for pinmux and GPIO hog nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device tree nodes for interrupt controllers should be named "interrupt-
controller", so rename the AGIC accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AON GPIO controller on Tegra194 currently only uses a single
interrupt, so remove the extra ones.
Signed-off-by: Thierry Reding <treding@nvidia.com>
SRAM nodes should be named sram@<unit-address> to match the bindings.
While at it, also remove the unneeded, custom compatible string for
SRAM partition nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
It's very difficult to describe string lists that can be in arbitrary
order using the json-schema based validation tooling. Since the OS is
not going to care either way, take the easy way out and reorder these
entries to match the order defined in the bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The address-bits and page-size properties that are currently used are
not valid properties according to the bindings. Use the address-width
and pagesize properties instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Use the preferred {id,vbus}-gpios over the {id,vbus}-gpio properties and
fix the ordering of compatible strings (most-specific ones should come
first).
Signed-off-by: Thierry Reding <treding@nvidia.com>
On Tegra186 and later, the BPMP is responsible for enabling/disabling
the PCIe related power supplies of the pad controller and there is no
need for the operating system to control them, so they can be removed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The external memory controller found on Tegra132 is not fully compatible
with the instantiation on Tegra124, so remove the corresponding string
from the list of compatible strings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.
While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the vendor-specific registers and clock for Qualcomm ICE (Inline
Crypto Engine) to the device tree node for the UFS host controller on
sdm845, so that the ufs-qcom driver will be able to use inline crypto.
Use a separate register range rather than extending the main UFS range
because there's a gap between the two, and the ICE registers are
vendor-specific. (Actually, the hardware claims that the ICE range also
includes the array of standard crypto configuration registers; however,
on this SoC the Linux kernel isn't permitted to access them directly.)
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20200710072013.177481-4-ebiggers@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Due to refactoring way back in bb53c820c5 ("arm64: stacktrace: avoid
listing stacktrace functions in stacktrace") the EXPORT_SYMBOL_GPL() for
save_stack_trace_tsk() is at the end of __save_stack_trace() rather than
the function it exports. Move it to the expected location.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20200710182402.50473-1-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Given that the contents of EFI runtime code and data regions are
provided by the firmware, as well as the DSDT, it is not unimaginable
that AML code exists today that accesses EFI runtime code regions using
a SystemMemory OpRegion. There is nothing fundamentally wrong with that,
but since we take great care to ensure that executable code is never
mapped writeable and executable at the same time, we should not permit
AML to create writable mapping.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Link: https://lore.kernel.org/r/20200626155832.2323789-3-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
AML uses SystemMemory opregions to allow AML handlers to access MMIO
registers of, e.g., GPIO controllers, or access reserved regions of
memory that are owned by the firmware.
Currently, we also allow AML access to memory that is owned by the
kernel and mapped via the linear region, which does not seem to be
supported by a valid use case, and exposes the kernel's internal
state to AML methods that may be buggy and exploitable.
On arm64, ACPI support requires booting in EFI mode, and so we can cross
reference the requested region against the EFI memory map, rather than
just do a minimal check on the first page. So let's only permit regions
to be remapped by the ACPI core if
- they don't appear in the EFI memory map at all (which is the case for
most MMIO), or
- they are covered by a single region in the EFI memory map, which is not
of a type that describes memory that is given to the kernel at boot.
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Link: https://lore.kernel.org/r/20200626155832.2323789-2-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sc7180.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593506712-24557-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sdm845.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593506712-24557-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
qup has a requirement to vote on the performance state of the CX domain
in sc7180 devices. Add OPP tables for these and also add power-domains
property for all qup instances for uart and spi.
i2c does not support scaling and uses a fixed clock.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593506712-24557-3-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
qup has a requirement to vote on the performance state of the CX domain
in sdm845 devices. Add OPP tables for these and also add power-domains
property for all qup instances for uart and spi.
i2c does not support scaling and uses a fixed clock.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1593506712-24557-2-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sc7180
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593769293-6354-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sdm845
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593769293-6354-3-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the "timing-adjustment" clock now that we know how it is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay on the MAC side (if needed).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
The "amlogic,meson-gx-pwrc-vpu" binding only supports the VPU power
domain, while actually there are more power domains behind that set of
registers. Switch to the new bindings so we can add more power domains
as needed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161211.23685-1-martin.blumenstingl@googlemail.com
Add the Khadas MCU node with active FAN thermal nodes for all the
Khadas VIM3 variants.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Link: https://lore.kernel.org/r/20200713065931.19845-1-narmstrong@baylibre.com
