Leo Liu
8b719b968f
drm/amdgpu: enable VCN4 PG and CG for VCN4_0_0
...
Most of the tiles can be power/clock gated.
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com >
Signed-off-by: Leo Liu <leo.liu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:56 -04:00
Evan Quan
b21348a28b
drm/amdgpu: enable fgcg for soc21
...
Enable Fine Grained Clock Gating on soc21 asics.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:54 -04:00
Evan Quan
390db4b84a
drm/amdgpu: enable GFX CGCG/CGLS for GC11.0.0
...
Enable GFX CGCG (coarse grained clockgating) and
CGLS (coarse grained light sleep) for GC11.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Likun Gao <Likun.Gao@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:54 -04:00
Jack Xiao
fd0ed91ae8
drm/amdgpu: correct cp doorbell range
...
1. move MES doorbell inside the mec doorbell range,
for mes belongs to mec block
2. setting the correct gfx/mec doorbell range, so that
fw can correctly detect gfx/compute work load to enter/exit
power saving state.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Tested-and-acked-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:53 -04:00
Jack Xiao
b608e785e1
drm/amdgpu: allocate doorbell index for mes kiq
...
Allocate a doorbell index for mes kiq queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 10:43:49 -04:00
Evan Quan
a6dec86840
drm/amdgpu/soc21: enable ATHUB and MMHUB PG
...
Enable ATHUB and MMHUB powergating.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-05-04 09:58:59 -04:00
Stanley.Yang
71199aa47b
drm/amdgpu: add soc21 common ip block v2
...
This adds soc21 common ip block support
Changed from v1:
Switch WREG32/RREG32_PCIE to use indirect reg access
helper for sco15 and onwards
Acked-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-04-28 17:48:40 -04:00
