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6 Commits

Author SHA1 Message Date
Johan Hovold
27da533af9 clk: qcom: gcc-sc8280xp: use retention for USB power domains 
Since commit d399723950 ("clk: qcom: gdsc: Fix the handling of
PWRSTS_RET support) retention mode can be used on sc8280xp to maintain
state during suspend instead of leaving the domain always on.

This is needed to eventually allow the parent CX domain to be powered
down during suspend.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220929161124.18138-1-johan+linaro@kernel.org
 2022-09-29 11:42:08 -05:00
Johan Hovold
f6d373ff28 clk: gcc-sc8280xp: keep USB power-domains always-on 
The Qualcomm DWC3 driver suspend implementation appears to be incomplete
for SC8280XP so keep the USB power domains always-on for now so that the
controller survives a suspend cycle.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805121250.10347-3-johan+linaro@kernel.org
 2022-08-18 14:12:03 -05:00
Johan Hovold
12d2a47693 clk: gcc-sc8280xp: keep PCIe power-domains always-on 
The Qualcomm PCIe driver does not yet implement suspend so to keep the
PCIe power domains always-on for now to avoid crashing during resume.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805121250.10347-2-johan+linaro@kernel.org
 2022-08-18 14:12:02 -05:00
Johan Hovold
9410fb9401 clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe 
Use the new phy-mux clock implementation for the PCIe pipe clock muxes
so that the pipe clock source is set to the QMP PHY PLL when the
downstream pipe clock is enabled and restored to the always-on XO when
it is again disabled.

This is needed to prevent the corresponding GDSC from hanging when
enabling or disabling the PCIe power domain, something which requires a
ticking source.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220628085707.16214-1-johan+linaro@kernel.org
 2022-06-29 21:53:23 -05:00
Johan Hovold
8d114b94fc clk: qcom: gcc-sc8280xp: use collapse-voting for PCIe GDSCs 
The PCIe GDSCs can be shared with other masters and should use the APCS
collapse-vote register when updating the power state.

This is specifically also needed to be able to disable power domains
that have been enabled by boot firmware using the vote register.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-4-johan+linaro@kernel.org
 2022-06-25 22:38:02 -05:00
Bjorn Andersson
d65d005f9a clk: qcom: add sc8280xp GCC driver 
Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
 2022-05-19 16:41:32 -05:00