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5642 Commits

Author SHA1 Message Date
Harry Wentland
b4f199c7b0 drm/amdgpu: Enable DC support for Navi10 
Enable the IP for navi10.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-22 09:34:07 -05:00
Xiaojie Yuan
76b743f45d drm/amd/display: use fixed-width data type for soc bounding box struct 
since it's firmware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Leo Li
57b3ec35d5 drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h 
DC needs to include the soc bounding box when initializing HW resources.

Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Harry Wentland
48321c3dde drm/amd/display: Read soc_bounding_box from gpu_info (v2) 
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:34 -05:00
Hawking Zhang
ccbf007b47 drm/amdgpu: initialize THM & CLK IP registers base address 
was missed before.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Marek Olšák
61af800fe7 drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2) 
Proper size is 0.

v2: squash in whitespace fixes (Ernst Sjöstrand)

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
tiancyin
4f56d9d412 drm/amdgpu: add new navi10 DIDs 
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Alex Deucher
6ad68a7e1f drm/amdgpu/gfx10: update to latest golden setting 
Fix UTCL1_CGTT_CLK_CTRL

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Leo Liu
450af30ce2 drm/amdgpu/VCN: enable indirect DPG SRAM mode 
This is default mode for VCN2.x now

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Leo Liu
dc8ae677c2 drm/amdgpu/VCN: implement indirect DPG SRAM mode 
SRAM will be programmed by PSP

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Leo Liu
a77b9fdf9a drm/amdgpu/VCN: add buffer for indirect SRAM usage 
This will be used later for indirect SRAM mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
86ddf3529e drm/amdgpu/psp: add new psp interface for vcn updating sram 
PSP leverages the existing fw loading function for vcn updating sram.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:33 -05:00
Jack Xiao
c76ff09bef drm/amdgpu/psp: convert ucode id to psp ucode id 
Convert ucode id to the corresponding psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Jack Xiao
6e72d8e9fb drm/amdgpu: add corresponding vcn ram ucode id 
Add VCN RAM ucode id in corresponding to psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Jack Xiao
68c0798cd9 drm/amdgpu/psp: add new VCN RAM ucode id to psp 
PSP supports to program vcn sram by ucode loading interface.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
157710ea4d drm/amdgpu: enable VCN2.0 DPG mode 
It will be the default for VCN2.x family

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
7282da0b3a drm/amdgpu/VCN2.0: add DPG pause mode 
Pause the DPG when not doing decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
bf4865b587 drm/amdgpu/VCN2.0: add DPG mode start and stop (v2) 
This is for using SRAM directly

v2: rebase (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
19c663fc77 drm/amdgpu/VCN2.0: add direct SRAM read and write 
This will be the basic and used for DPG mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Leo Liu
b3ef5ce037 drm/amdgpu/VCN2.0 remove unused Macro and declaration 
Just for cleanup

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Kevin Wang
6f6a7bba69 drm/amd/powerplay: fix deadlock issue for smu_force_performance_level 
the smu->mutex is internal lock resource in sw-smu, some functions will use
it at the same time, so it maybe will cause deadlock issue.
this patch fix this issue in smu_force_performance_level function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Jack Xiao
3ebab625e6 drm/amd: the data retured from PRT is expected to be 0 
The dummy page for returning from PRT resides inside system memory,
need set system flag bit in VM_L2_CNTL.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
tiancyin
b1fa87a48e drm/amdgpu/gfx10: update gfx golden settings 
add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL,
update registers: mmDB_DEBUG4, mmUTCL1_CTRL

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:32 -05:00
Kevin Wang
576851345b drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk) 
remove smu callback: get_mclk, get_sclk.
because the function smu_get_dpm_freq_range has the same function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Tao Zhou
462a70d87e drm/amdgpu: correct reference clock value on navi10 
remove the divisor 4

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:31 -05:00
Kevin Wang
db439ca21b drm/amd/powerplay: add function force_clk_levels for navi10 
add sysfs interface of force_clk_levels sysfs for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Kevin Wang
b1e7e22419 drm/amd/powerplay: add function print_clk_levels for navi10 
add sysfs interface of print_clk_levels sysfs for navi10.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
bbd7a65350 drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume 
CSIB BO is required to be pinned down to guarantee
bo is always valid when resume, and to be unpinned it
so that its content can be saved during suspend.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
2c195b6cac drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactive 
The following KIQ ring test could guarantee the previous unmap
has been done.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Jack Xiao
e17a512a18 drm/amdgpu: RLC must be disabled after SMU when S3 on navi 
SMU requires to interact with RLC when disable all features,
so RLC shouldn't be disabled ahead of SMU.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:29 -05:00
Leo Liu
863dd269fa drm/amdgpu/VCN2.0: remove powergating for UVDW tile 
No UVDW tile any more from VCN2.0, so mark out related fields.

It fixes error:
"[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa"

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Xiaojie Yuan
c39f3da4e2 drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring is disabled 
gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is
enabled, so should gfx_v10_0_kiq_disable_kgq().

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Xiaojie Yuan
ec171a9302 drm/amdgpu/gfx10: drop redundant se/sh selection 
we already selected se/sh at the beginning of the for loop

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
77657ad1ec drm/amdgpu/mes10.1: enable mes FW backdoor loading 
It enables MES FW backdoor loading in ip block functions.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
5c264af735 drm/amdgpu/mes10.1: implement mes enablement function 
After MES firmware gets loaded, it enables MES engine starting execution.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
fb19a68df2 drm/amdgpu/mes10.1: implement MES firmware backdoor loading 
It implements MES firmware backdoor loading.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
71c5794188 drm/amdgpu/mes10.1: implement ucode buffers destruction 
Free ucode GPU buffers.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
85c90e9b54 drm/amdgpu/mes10.1: upload mes data ucode to gpu buffer 
Allocate GPU buffer and upload mes data ucode to the buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
02b6114948 drm/amdgpu/mes10.1: upload mes ucode to gpu buffer 
Allocate GPU buffer and upload ucode firmware to the buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
086981052b drm/amdgpu/mes10.1: implement ucode CPU buffer destruction 
It implements the CPU buffer destruction of ucode.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
298d05460c drm/amdgpu/mes10.1: load mes firmware file to CPU buffer 
It requests MES firmware binary and uploads to CPU buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
5aa91248c0 drm/amdgpu/mes10.1: add mes firmware info fields 
The newly added fields is to store mes firmware related information.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:28 -05:00
Jack Xiao
7f785e7843 drm/amdgpu/ucode: add mes firmware file support 
The newly added firmware struct is for mes firmware file.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
186b0ca282 drm/amdgpu/ucode: add the definitions of MES ucode and ucode data 
MES requires two seperate firmwares: ucode and ucode data.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
37809f5529 drm/amdgpu/sdma5: incorrect variable type for gpu address 
Incorrect programming with 64bit gpu address assignment for
32bit variable.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
tiancyin
278b6fba22 drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples test 
[why]
When page fault happens, it could lead to sdma hang is RESP_MODE =
0 for non-PRT case.

[how]
Setting  SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt.

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
6ff687319f drm/amdgpu/nv: set vcn pg flag 
Enable VCN power gating by default.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
6e4cb4e8b3 drm/amdgpu: enable vcn dpm scheme for navi 
On navi1x, vcn dpm scheme was merged into powergating scheme.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
0b8794e252 drm/amdgpu/vcn2: don't access register when power gated 
It will cause bus hang to access register UVD_STATUS
when VCN is in the state of power gated.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00
Jack Xiao
c113ba157f drm/amdgpu/vcn2: notify SMU power up/down VCN 
For sw control power gating, it needs notify SMU to power up/down VCN
when enter/exit working state.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-06-21 18:59:27 -05:00