This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch changes the uImage target so that it generates a wrapped
compressed vmlinux, rather than a wrapped zImage. The previous version
matched the ARM, this version matches the PPC. However I would question
how useful a self decompressing image is with a boot loader which does
decompression, so I think this is more useful. I also feel it matches
the descrition in the help text ("Compressed kernel image") better.
Signed-off-by: Thomas Betker <thomas.betker@5etech.eu>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This saves us from having to use kmalloc() for the fixmap entries,
which is needed early for the uncached fixmap.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This implements kernel-level atomic rollback built on top of gUSA,
as an alternative non-IRQ based atomicity method. This is generally
a faster method for platforms that are lacking the LL/SC pairs that
SH-4A and later use, and is only supportable on legacy cores.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Shoves a magic word in to the empty_zero_page section for the
bootloader to work out whether to start the kernel in 29-bit
or 32-bit mode.
[ Renesas CPUs already take care of the initial PMB mappings entirely
in hardware and decide on 29-bit/32-bit physical depending on which
pin powered up the CPU, so this is mostly for ST parts. -- PFM ].
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
mem= can't be used to grow the size of kernel memory, so provide a
warning to that effect.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds support for the SH7263 (SH-2A) CPU.
This particular CPU is a superset of SH7203, adding some additional
peripheral blocks and hooking up additional (reserved on SH7203)
vectors in the INTC block.
No visibly nasty surprises, yet..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This was using the absolute path, which was confusing the make target.
Switch it to just 'zImage', as per powerpc.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This is trivial, in that they're both effectively the same for the base
relocations anyways. SH-5 doesn't need the unaligned bits, and has a
few extra relocations, which are never hit on non-SH5 parts.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (54 commits)
MAINTIANERS: just use Mike gmail e-mail for contact and pawn the serial driver off onto Sonic
[Blackfin] arch: remove old I2C BF54x porting.
[Blackfin] arch: Add the semtimedop syscall. Upstream uClibc doesn't compile without it.
[Blackfin] arch: fix bug kernel boot message: memory information is not reasonable
[Blackfin] arch: use common flash driver to setup partitions rather than the bf5xx-flash driver
[Blackfin] arch: Fix bug - kernel build with Debug option enabled fails to boot up
[Blackfin] arch: Fix bug Only RTC interrupt can wake up deeper sleep core.
[Blackfin] arch: Add proper SW System Reset delay sequence
[Blackfin] arch: Update copyright date
[Blackfin] arch: GPIO API cleanup and anomaly update
[Blackfin] arch: Fix BUG gpio_direction_output API is not compatitable with GENERIC_GPIO API interface
[Blackfin] arch: Initial checkin of the memory protection support.
[Blackfin] arch: set_bfin_dma_config shouldnt set SYNC or RESTART by default - add argument or option
[Blackfin] arch: Add some comments - fix semicolons
[Blackfin] arch: move all code related to CPLB handling into a new subdirectory under kernel/
[Blackfin] arch: print out list of modules if kernel is crashing and tell people if the kernel is tainted
[Blackfin] arch: enable generic GPIO based I2C driver in STAMP-BF533, EZKIT-BF533 and EZKIT-BF561 boards
[Blackfin] arch: Don't oops_in_progress if single step is comming from the kernel
[Blackfin] arch: Fix BUG - kernel sometimes would stuck with KEYBOARD_GPIO on
[Blackfin] arch: update to latest anomaly sheets
...
From: Nicolas Ferre <nicolas.ferre@rfo.atmel.com>
On the at92sam9263ek board, tell the input subsystem about the buttons.
This patch is taken from Andrew Victor's at91 patchset, then updated to
match the latest kernel code and to use labels printed on the board.
Also update the at91sam9261ek buttons to cope with input changes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Convert the i2c-au1550 bus driver to platform driver, and
register a platform device for the Alchemy Db/Pb series of
boards.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Add polling I2C transfer implementation for PXA I2C. This is needed
for cases where I2C transactions have to occur at times interrups are
disabled.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Acked-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Move the tps65010 header file from the OMAP arch directory to the
more generic <linux/i2c/...> directory, and remove the spurious
dependency of this driver on OMAP.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Migrate all ixp4xx devices to the bitbanging I2C bus driver utilizing
the arch-neutral GPIO API (linux/i2c-gpio.h).
Tested by the nslu2-linux and openwrt projects in public firmware releases.
Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
Acked-by: Rod Whitby <rod@whitby.id.au>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
This patch contains the scheduled removal of legacy I2C RTC drivers with
replacement drivers.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
The kprobes code is already able to cope with reentrant probes, so its
handler must be called outside of the region protected by undef_lock.
If ever this lock is released when handlers are called then this commit
could be reverted.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
If kprobes installs a breakpoint on a "stmdb sp!, {...}" instruction,
and then single-step it by simulation from the exception context, it will
corrupt the saved regs on the stack from the previous context.
To avoid this, let's add an optional parameter to the svc_entry macro
allowing for a hole to be created on the stack before saving the
interrupted context, and use it in the undef_svc handler when kprobes
is enabled.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This is a full implementation of Kprobes including Jprobes and
Kretprobes support.
This ARM implementation does not follow the usual kprobes double-
exception model. The traditional model is where the initial kprobes
breakpoint calls kprobe_handler(), which returns from exception to
execute the instruction in its original context, then immediately
re-enters after a second breakpoint (or single-stepping exception)
into post_kprobe_handler(), each time the probe is hit.. The ARM
implementation only executes one kprobes exception per hit, so no
post_kprobe_handler() phase. All side-effects from the kprobe'd
instruction are resolved before returning from the initial exception.
As a result, all instructions are _always_ effectively boosted
regardless of the type of instruction, and even regardless of whether
or not there is a post-handler for the probe.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Quentin Barnes <qbarnes@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This is the code implementing instruction single-stepping for kprobes
on ARM.
To get around the limitation of no Next-PC and no hardware single-
stepping, all kprobe'd instructions are split into three camps:
simulation, emulation, and rejected. "Simulated" instructions are
those instructions which behavior is reproduced by straight C code.
"Emulated" instructions are ones that are copied, slightly altered
and executed directly in the instruction slot to reproduce their
behavior. "Rejected" instructions are ones that could be simulated,
but work hasn't been put into simulating them. These instructions
should be very rare, if not unencountered, in the kernel. If ever
needed, code could be added to simulate them.
One might wonder why this and the ptrace singlestep facility are not
sharing some code. Both approaches are fundamentally different because
the ptrace code regains control after the stepped instruction by installing
a breakpoint after the instruction itself, and possibly at the location
where the instruction might be branching to, instead of simulating or
emulating the target instruction.
The ptrace approach isn't suitable for kprobes because the breakpoints
would have to be moved back, and the icache flushed, everytime the
probe is hit to let normal code execution resume, which would have a
significant performance impact. It is also racy on SMP since another
CPU could, with the right timing, sail through the probe point without
being caught. Because ptrace single-stepping always result in a
different process to be scheduled, the concern for performance is much
less significant.
On the other hand, the kprobes approach isn't (currently) suitable for
ptrace because it has no provision for proper user space memory
protection and translation, and even if that was implemented, the gain
wouldn't be worth the added complexity in the ptrace path compared to
the current approach.
So, until kprobes does support user space, both kprobes and ptrace are
best kept independent and separate.
Signed-off-by: Quentin Barnes <qbarnes@gmail.com>
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
registers are retained during standby mode, thus it's not necessary
to save/restore and checksum
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When PXA27x wakes up, tick_resume_oneshot() tries to set a timer
interrupt to occur immediately. Since PXA27x requires at least
MIN_OSCR_DELTA, this causes us to flag an error.
tick_program_event() then increments the next event time by
min_delta_ns. However, by the time we get back to programming
the next event, the OSCR has incremented such that we fail again.
We repeatedly retry, but the OSCR is too fast for us - we never
catch up, so we never break out of the loop - resulting in us
never apparantly resuming.
Fix this by doubling min_delta_ns.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The PXA manuals indicate that when in standby or sleep modes, clocks to
peripherals are shut off by the processor itself. Eg:
PXA270 standby: "In standby mode, all clocks are disabled except those
for the power manager and the RTC."
PXA270 sleep: "In sleep mode, all clocks are disabled to the processor
and to all peripherals except the RTC."
PXA255 sleep: "In Sleep Mode, all processor and peripheral clocks are
disabled, except the RTC."
Therefore, it should be safe to leave the clock enable register alone
prior to entering low power modes for these SoCs.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Wakeup sources on PXA3 are enabled at two levels. First, the MFP
configuration has to be set to enable which edges a specific pin
will trigger a wakeup. The pin also has to be routed to a functional
unit. Lastly, the functional unit must be enabled as a wakeup source
in the appropriate AD*ER registers (AD2D0ER for standby resume.)
This doesn't fit well with the IRQ wake scheme - we currently do a
best effort conversion from IRQ numbers to functional unit wake enable
bits. For instance, there's several USB client related enable bits but
there's no corresponding IRQs to determine which you'd want. Conversely,
there's a single enable bit covering several functional units.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Hook the MFP code into the power management code so that the MFPs can
be reconfigured when suspending and resuming. However, note the FIXME
- low power mode MFP configuration may depend on the system state being
entered.
Also note that we have to clear any detected edge events prior to
entering a low power mode - otherwise we immediately wake up.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There are two reasons for making the MFP configuration to be processor
independent, i.e. removing the relationship of configuration bits with
actual MFPR register settings:
1. power management sometimes requires the MFP to be configured
differently when in run mode or in low power mode
2. for future integration of pxa{25x,27x} GPIO configurations
The modifications include:
1. introducing of processor independent MFP configuration bits, as
defined in [include/asm-arm/arch-pxa/mfp.h]:
bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
bit 10..12 - Alternate Function Selection
bit 13..15 - Drive Strength
bit 16..18 - Low Power Mode State
bit 19..20 - Low Power Mode Edge Detection
bit 21..22 - Run Mode Pull State
and so on,
2. moving the processor dependent code from mfp.h into mfp-pxa3xx.h
3. cleaning up of the MFPR bit definitions
4. mapping of processor independent MFP configuration into processor
specific MFPR register settings is now totally encapsulated within
pxa3xx_mfp_config()
5. using of "unsigned long" instead of invented type of "mfp_cfg_t"
according to Documentation/CodingStyle Chapter 5, usage of this
in platform code will be slowly removed in later patches
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
pxa3xx_mfp_set_xxx() functions are originally provided for overwriting
MFP configurations performed by pxa3xx_mfp_config(), the usage of such
a dirtry trick is not recommended, since there is currently no user of
these functions, they are safely removed
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PXA3 has a different memory controller from PXA2 platforms. Avoid
clashing definitions by moving the PXA2 definitions to pxa2xx-regs.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The mapping for physical address 0x48000000 is not sufficient
to allow access to the dynamic memory controller configuration
registers on PXA3. These registers need to be accessed to
reconfigure the SDRAM when waking from a low power mode.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is to add the third mmc controller support _only_
for pxa310.
On zylonite, the third controller support one slot.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is to add the second mmc controller support for pxa3xx.
It's valid for pxa3[0|1|2]0.
On zylonite, the second controller has no slot.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patchis to add the first mmc controller support for pxa3xx.
It's valid for pxa3[0|1|2]0.
On zylonite, the first controller supports two slots, this patch
only support the first one right now.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Considering that generic.c is getting more and more bloated by device
information, moving that part out side will be much cleaner.
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch is to move pxamci DMA specific code to corresponding
platform layer because using DRCMRRXMMC/DRCMRTXMMC in pxamci.c makes
the driver code dedicated to platform which is not extensible.
It is applicable to all pxa platforms.
Signed-off-by: Bridge Wu <bridge.wu@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There have been patches hanging around for ages to add support for
cpufreq to PXA255 processors. It's about time we applied one.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Initialise the SSP driver at arch_initcall() time, so it's available
for other drivers to use it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Only register the "cpld_irq" sysclass for mainstone/lubbock if we're
running on one of those platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1. make pxa2xx_spi.c use ssp_request() and ssp_free() to get the common
information of the designated SSP port.
2. remove those IRQ/memory request code, ssp_request() has done that for
the driver
3. the SPI platform device is thus made psuedo, no resource (memory/IRQ)
has to be defined, all will be retreived by ssp_request()
4. introduce ssp_get_clk_div() to handle controller difference in clock
divisor setting
5. use clk_xxx() API for clock enable/disable, and clk_get_rate() to
handle the different SSP clock frequency between different processors
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
