Pull ARMv4T/v5 multiplatform support from Arnd Bergmann:
"This series has been 12 years in the making, it mostly finishes the
work that was started with the founding of Linaro to clean up platform
support in the kernel.
The largest change here is a cleanup of the omap1 platform, which is
the final ARM machine type to get converted to the common-clk
subsystem. All the omap1 specific drivers are now made independent of
the mach/*.h headers to allow the platform to be part of a generic
ARMv4/v5 multiplatform kernel.
The last bit that enables this support is still missing here while we
wait for some last dependencies to make it into the mainline kernel
through other subsystems.
The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost
at the point of allowing multiplatform kernels, this work gets
completed here along with a few additional cleanup. At the same time,
the s3c24xx and s3c64xx are now deprecated and expected to get removed
in the future.
The PXA and OMAP1 bits are in a separate branch because of
dependencies. Once both branches are merged, only the three Intel
StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100)
need separate kernels, and there are no plans to include these"
* tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits)
ARM: ixp4xx: Consolidate Kconfig fixing issue
ARM: versatile: Add missing of_node_put in dcscb_init
ARM: config: Refresh IXP4xx config after multiplatform
ARM: omap1: add back omap_set_dma_priority() stub
ARM: omap: fix missing declaration warnings
ARM: omap: fix address space warnings from sparse
ARM: spear: remove include/mach/ subdirectory
ARM: davinci: remove include/mach/ subdirectory
ARM: omap2: remove include/mach/ subdirectory
integrator: remove empty ap_init_early()
ARM: s3c: fix include path
MAINTAINERS: omap1: Add Janusz as an additional maintainer
ARM: omap1: htc_herald: fix typos in comments
ARM: OMAP1: fix typos in comments
ARM: OMAP1: clock: Remove noop code
ARM: OMAP1: clock: Remove unused code
ARM: OMAP1: clock: Fix UART rate reporting algorithm
ARM: OMAP1: clock: Fix early UART rate issues
ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF
ARM: omap1: fix build with no SoC selected
...
This SPI driver adds support for the Aspeed static memory controllers
of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.
* AST2600 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. Only supports SPI type flash memory
. different segment register interface
. single, dual and quad mode.
* AST2600 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. different segment register interface
. single, dual and quad mode.
* AST2500 Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. supports SPI type flash memory (CE0-CE1)
. CE2 can be of NOR type flash but this is not supported by the driver
. single, dual mode.
* AST2500 SPI Flash Controller (SPI1 and SPI2)
. host firmware
. 2 chip select pins (CE0 ~ CE1)
. single, dual mode.
* AST2400 New Static Memory Controller (also referred as FMC)
. BMC firmware
. New register set
. 5 chip select pins (CE0 ∼ CE4)
. supports NOR flash, NAND flash and SPI flash memory.
. single, dual and quad mode.
Each controller has a memory range on which flash devices contents are
mapped. Each device is assigned a window that can be changed at bootime
with the Segment Address Registers.
Each SPI flash device can then be accessed in two modes: Command and
User. When in User mode, SPI transfers are initiated with accesses to
the memory segment of a device. When in Command mode, memory
operations on the memory segment of a device generate SPI commands
automatically using a Control Register for the settings.
This initial patch adds support for User mode. Command mode needs a little
more work to check that the memory window on the AHB bus fits the device
size. It will come later when support for direct mapping is added.
Single and dual mode RX transfers are supported. Other types than SPI
are not supported.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org
Signed-off-by: Mark Brown <broonie@kernel.org>
1.Since it would be dangerous to specify a newer SoC's compatible
string as the fallback of an older SoC's compatible string, we
add support for the "ingenic,jz4775-spi" compatible string in
the driver.
This will permit to support the JZ4775 by having:
compatible = "ingenic,jz4775-spi";
Instead of doing:
compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi";
2.Add support for probing the spi-ingenic driver on the X1000 SoC
from Ingenic. From the X1000 SoC onwards, the maximum frequency
allowed by the SSI module of Ingenic SoCs has been changed from
54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info"
to set different maximum frequency values.
3.Add support for probing the spi-ingenic driver on the X2000 SoC
from Ingenic. The X2000 SoC has only one native chip select line,
so "max_native_cs" is introduced in "jz_soc_info" to set different
maximum number of native chip select lines.
4.Because of the introduction of support for the X-series SoCs, the
current driver is not only applicable to the JZ-series SoCs, so
the description texts has been modified to avoid misunderstanding.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The driver has always had a FIXME about this, and it seems
like this trivial code move avoids a mach header inclusion,
so just do it.
With that out of the way, and the header file inclusions
changed to global files, the driver can also be compile-tested
on other platforms.
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull MTD updates from Miquel Raynal:
"There has been a lot of activity in the MTD subsystem recently, with a
number of SPI-NOR cleanups as well as the introduction of ECC engines
that can be used by SPI controllers (hence a few SPI patches in here).
Core MTD changes:
- Replace the expert mode symbols with a single helper
- Fix misuses of of_match_ptr()
- Remove partid and partname debugfs files
- tests: Fix eraseblock read speed miscalculation for lower partition
sizes
- TRX parser: Allow to use on MediaTek MIPS SoCs
MTD driver changes:
- spear_smi: use GFP_KERNEL
- mchp48l640: Add SPI ID table
- mchp23k256: Add SPI ID table
- blkdevs: Avoid soft lockups with some mtd/spi devices
- aspeed-smc: Improve probe resilience
Hyperbus changes:
- HBMC_AM654 should depend on ARCH_K3
NAND core changes:
- ECC:
- Add infrastructure to support hardware engines
- Add a new helper to retrieve the ECC context
- Provide a helper to retrieve a pilelined engine device
NAND-ECC changes:
- Macronix ECC engine:
- Add Macronix external ECC engine support
- Support SPI pipelined mode
- Make two read-only arrays static const
- Fix compile test issue
Raw NAND core changes:
- Fix misuses of of_match_node()
- Rework of_get_nand_bus_width()
- Remove of_get_nand_on_flash_bbt() wrapper
- Protect access to rawnand devices while in suspend
- bindings: Document the wp-gpios property
Rax NAND controller driver changes:
- atmel: Fix refcount issue in atmel_nand_controller_init
- nandsim:
- Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
- Merge repeat codes in ns_switch_state
- Replace overflow check with kzalloc to single kcalloc
- rockchip: Fix platform_get_irq.cocci warning
- stm32_fmc2: Add NAND Write Protect support
- pl353: Set the nand chip node as the flash node
- brcmnand: Fix sparse warnings in bcma_nand
- omap_elm: Remove redundant variable 'errors'
- gpmi:
- Support fast edo timings for mx28
- Validate controller clock rate
- Fix controller timings setting
- brcmnand:
- Add BCMA shim
- BCMA controller uses command shift of 0
- Allow platform data instantation
- Add platform data structure for BCMA
- Allow working without interrupts
- Move OF operations out of brcmnand_init_cs()
- Avoid pdev in brcmnand_init_cs()
- Allow SoC to provide I/O operations
- Assign soc as early as possible
Onenand changes:
- Check for error irq
SPI-NAND core changes:
- Delay a little bit the dirmap creation
- Create direct mapping descriptors for ECC operations
SPI-NAND driver changes:
- macronix: Use random program load
SPI NOR core changes:
- Move vendor specific code out of the core into vendor drivers.
- Unify all function and object names in the vendor modules.
- Make setup() callback optional to improve readability.
- Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
declaration.
SPI changes:
- Macronix SPI controller:
- Fix the transmit path
- Create a helper to configure the controller before an operation
- Create a helper to ease the start of an operation
- Add support for direct mapping
- Add support for pipelined ECC operations
- spi-mem:
- Introduce a capability structure
- Check the controller extra capabilities
- cadence-quadspi/mxic: Provide capability structures
- Kill the spi_mem_dtr_supports_op() helper
- Add an ecc parameter to the spi_mem_op structure
Binding changes:
- Dropped mtd/cortina,gemini-flash.txt
- Convert BCM47xx partitions to json-schema
- Vendor prefixes: Clarify Macronix prefix
- SPI NAND: Convert spi-nand description file to yaml
- Raw NAND chip: Create a NAND chip description
- Raw NAND controller:
- Harmonize the property types
- Fix a comment in the examples
- Fix the reg property description
- Describe Macronix NAND ECC engine
- Macronix SPI controller:
- Document the nand-ecc-engine property
- Convert to yaml
- The interrupt property is not mandatory"
* tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits)
mtd: nand: ecc: mxic: Fix compile test issue
mtd: nand: mxic-ecc: make two read-only arrays static const
mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3
mtd: core: Remove partid and partname debugfs files
dt-bindings: mtd: partitions: convert BCM47xx to the json-schema
mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes
mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init
mtd: rawnand: rockchip: fix platform_get_irq.cocci warning
mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set
mtd: spi-nor: renumber flags
mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
mtd: spi-nor: spansion: rename vendor specific functions and defines
mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
mtd: spi-nor: move all spansion specifics into spansion.c
mtd: spi-nor: spansion: slightly rework control flow in late_init()
mtd: spi-nor: micron-st: rename vendor specific functions and defines
mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
mtd: spi-nor: move all micron-st specifics into micron-st.c
mtd: spi-nor: xilinx: correct the debug message
mtd: spi-nor: xilinx: rename vendor specific functions and defines
...
Merge series from Mika Westerberg <mika.westerberg@linux.intel.com>:
Based on discussion on the patch I sent some time ago here:
http://lists.infradead.org/pipermail/linux-mtd/2021-June/086867.html
it turns out that the preferred way to deal with the SPI flash controller
drivers is through SPI MEM which is part of Linux SPI subsystem.
This series does that for the intel-spi driver. This also renames the
driver to follow the convention used in the SPI subsystem. The first patch
improves the write protection handling to be slightly more safer. The
following two patches do the conversion itself. Note the Intel SPI flash
controller only allows commands such as read, write and so on and it
internally uses whatever addressing etc. it figured from the SFDP on the
flash device.
base-commit: e783362eb5
Some SPI-NAND chips do not have a proper on-die ECC engine providing
error correction/detection. This is particularly an issue on embedded
devices with limited resources because all the computations must
happen in software, unless an external hardware engine is provided.
These external engines are new and can be of two categories: external
or pipelined. Macronix is providing both, the former being already
supported. The second, however, is very SoC implementation dependent
and must be instantiated by the SPI host controller directly.
An entire subsystem has been contributed to support these engines which
makes the insertion into another subsystem such as SPI quite
straightforward without the need for a lot of specific functions.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20220202144536.393792-1-miquel.raynal@bootlin.com
This patch series adds support for Cadence's XSPI controller.
It supports 3 work modes.
1. ACMD (auto command) work mode
ACMD name is because it uses auto command engine in the controller.
It further has 2 modes PIO and CDMA (command DMA).
The CDMA work mode is dedicated for high-performance application
where very low software overhead is required. In this mode the
Command Engine is programmed by the series of linked descriptors
stored in system memory. These descriptors provide commands to execute
and store status information for finished commands.
The PIO mode work mode is dedicated for single operation where
constructing a linked list of descriptors would require too
much effort.
2. STIG (Software Triggered Instruction Generator) work mode
In STIG mode, controller sends low-level instructions to memory.
Each instruction is 128-bit width. There is special instruction
DataSequence which carries information about data phase.
Driver uses Slave DMA interface to transfer data as only this
interface can be used in STIG work mode.
3. Direct work mode
This work mode allows sending data without invoking any command through
the slave interface.
Currently only STIG work mode is enabled, remaining work modes will
be added later.
Changes since v5:
1. Added adjust_op_size to adjust op size according to sdma size.
Changes since v4:
1. Changed reg region names and lengths as suggested by Rob.
Changes since v3:
1. Removed ACMD PIO mode.
2. Return IRQ_HANDLED only for handled interrupts.
3. DT binding changes.
Changes since v2:
1. Removed extra lock around exec_op.
2. Removed PHY parameters setting from the driver, those will be
handled by bootstrap pins available in the controller.
Changes since v1:
1. Use ACMD PIO work mode for NOR read, program and erase operations,
for everything else use STIG(Software Triggered Instruction
Generator) work mode.
2. Changes suggested by Lukas.
Parshuram Thombare (2):
spi: cadence: add dt-bindings documentation for Cadence XSPI
controller
spi: cadence: add support for Cadence XSPI controller
.../devicetree/bindings/spi/cdns,xspi.yaml | 77 +++
drivers/spi/Kconfig | 12 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-cadence-xspi.c | 640 +++++++++++++++++++++
4 files changed, 730 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/cdns,xspi.yaml
create mode 100644 drivers/spi/spi-cadence-xspi.c
--
2.7.4
This patch adds driver for Cadence's XSPI controller.
It supports 3 work modes.
1. ACMD (auto command) work mode
ACMD name is because it uses auto command engine in the controller.
It further has 2 modes PIO and CDMA (command DMA).
The CDMA work mode is dedicated for high-performance application
where very low software overhead is required. In this mode the
Command Engine is programmed by the series of linked descriptors
stored in system memory. These descriptors provide commands to execute
and store status information for finished commands.
The PIO mode work mode is dedicated for single operation where
constructing a linked list of descriptors would require too
much effort.
2. STIG (Software Triggered Instruction Generator) work mode
In STIG mode, controller sends low-level instructions to memory.
Each instruction is 128-bit width. There is special instruction
DataSequence which carries information about data phase.
Driver uses Slave DMA interface to transfer data as only this
interface can be used in STIG work mode.
3. Direct work mode
This work mode allows sending data without invoking any command through
the slave interface.
Currently only STIG work mode is enabled, remaining work modes will
be added later.
Signed-off-by: Konrad Kociolek <konrad@cadence.com>
Signed-off-by: Jayshri Pawar <jpawar@cadence.com>
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/1632038734-23999-1-git-send-email-pthombar@cadence.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Pull spi updates from Mark Brown:
"The main focus of this release from a framework point of view has been
spi-mem where we've acquired support for a few new hardware features
which enable better performance on suitable hardware.
Otherwise mostly thanks to Arnd's cleanup efforts on old platforms
we've removed several obsolete drivers which just about balance out
the newer drivers we've added this cycle.
Summary:
- Allow drivers to flag if they are unidirectional.
- Support for DTR mode and hardware acceleration of dummy cycles in
spi-mem.
- Support for Allwinder H616, Intel Lightning Mountain, nVidia Tegra
QuadSPI, Realtek RTL838x and RTL839x.
- Removal of obsolete EFM32, Txx9 and SIRF Prima and Atlas drivers"
* tag 'spi-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (76 commits)
spi: Skip zero-length transfers in spi_transfer_one_message()
spi: dw: Avoid stack content exposure
spi: cadence-quadspi: Use spi_mem_dtr_supports_op()
spi: spi-mem: add spi_mem_dtr_supports_op()
spi: atmel-quadspi: Disable the QSPI IP at suspend()
spi: pxa2xx: Add IDs for the controllers found on Intel Lynxpoint
spi: pxa2xx: Fix the controller numbering for Wildcat Point
spi: Change provied to provided in the file spi.h
spi: mediatek: add set_cs_timing support
spi: support CS timing for HW & SW mode
spi: add power control when set_cs_timing
spi: stm32: make spurious and overrun interrupts visible
spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC
spi: stm32: defer probe for reset
spi: stm32: driver uses reset controller only at init
spi: stm32h7: ensure message are smaller than max size
spi: stm32: use bitfield macros
spi: stm32: do not mandate cs_gpio
spi: stm32: properly handle 0 byte transfer
spi: clps711xx: remove redundant white-space
...
The Ericsson U300 platform was one of two ARM929 based SoC platforms for
mobile phones in ST-Ericsson after the merger of Ericsson with ST-NXP
into ST-Ericsson, the other one being the ST Nomadik.
The platform was not widely adopted in Linux based systems and was
replaced with the far superior ST-Ericsson U8500 in 2011, but Linus
Walleij kept maintaining the code for the whole time.
Linus continues to use the Nomadik machine, but decided to drop
u300 from the kernel as part of this year's spring cleaning.
Thanks for having maintained it all these years.
Cc: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/lkml/CACRpkdbJkiHR9FSfJTH_5d_qRU1__dRXHM1TL40iqNRKbGQfrQ@mail.gmail.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull ARM SoC platform updates from Olof Johansson:
"SoC changes, a substantial part of this is cleanup of some of the
older platforms that used to have a bunch of board files.
In particular:
- Remove non-DT i.MX platforms that haven't seen activity in years,
it's time to remove them.
- A bunch of cleanup and removal of platform data for TI/OMAP
platforms, moving over to genpd for power/reset control (yay!)
- Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
closer to multiplatform support (not quite there yet, but getting
close).
There are a few other changes too, smaller fixlets, etc. For new
platform support, the primary ones are:
- New SoC: Hisilicon SD5203, ARM926EJ-S platform.
- Cpufreq support for i.MX7ULP"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
ARM: mstar: Select MStar intc
ARM: stm32: Replace HTTP links with HTTPS ones
ARM: debug: add UART early console support for SD5203
ARM: hisi: add support for SD5203 SoC
ARM: omap3: enable off mode automatically
clk: imx: imx35: Remove mx35_clocks_init()
clk: imx: imx31: Remove mx31_clocks_init()
clk: imx: imx27: Remove mx27_clocks_init()
ARM: imx: Remove unused definitions
ARM: imx35: Retrieve the IIM base address from devicetree
ARM: imx3: Retrieve the AVIC base address from devicetree
ARM: imx3: Retrieve the CCM base address from devicetree
ARM: imx31: Retrieve the IIM base address from devicetree
ARM: imx27: Retrieve the CCM base address from devicetree
ARM: imx27: Retrieve the SYSCTRL base address from devicetree
ARM: s3c64xx: bring back notes from removed debug-macro.S
ARM: s3c24xx: fix Wunused-variable warning on !MMU
ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
MAINTAINERS: mark linux-samsung-soc list non-moderated
ARM: imx: Remove remnant board file support pieces
...
Baikal-T1 is equipped with three DW APB SSI-based MMIO SPI controllers.
Two of them are pretty much normal: with IRQ, DMA, FIFOs of 64 words
depth, 4x CSs, but the third one as being a part of the Baikal-T1 System
Boot Controller has got a very limited resources: no IRQ, no DMA, only a
single native chip-select and Tx/Rx FIFO with just 8 words depth
available. In order to provide a transparent initial boot code execution
the Boot SPI controller is also utilized by an vendor-specific IP-block,
which exposes an SPI flash direct mapping interface. Since both direct
mapping and SPI controller normal utilization are mutual exclusive only
one of these interfaces can be used to access an external SPI slave
device. That's why a dedicated mux is embedded into the System Boot
Controller. All of that is taken into account in the Baikal-T1-specific DW
APB SSI glue driver implemented by means of the DW SPI core module.
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20201007235511.4935-22-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Aside from the synchronous Tx-Rx mode, which has been utilized to create
the normal SPI transfers in the framework of the DW SSI driver, DW SPI
controller supports Tx-only and EEPROM-read modes. The former one just
enables the controller to transmit all the data from the Tx FIFO ignoring
anything retrieved from the MISO lane. The later mode is so called
write-then-read operation: DW SPI controller first pushes out all the data
from the Tx FIFO, after that it'll automatically receive as much data as
has been specified by means of the CTRLR1 register. Both of those modes
can be used to implement the memory operations supported by the SPI-memory
subsystem.
The memory operation implementation is pretty much straightforward, except
a few peculiarities we have had to take into account to make things
working. Since DW SPI controller doesn't provide a way to directly set and
clear the native CS lane level, but instead automatically de-asserts it
when a transfer going on, we have to make sure the Tx FIFO isn't empty
during entire Tx procedure. In addition we also need to read data from the
Rx FIFO as fast as possible to prevent it' overflow with automatically
fetched incoming traffic. The denoted peculiarities get to cause even more
problems if DW SSI controller is equipped with relatively small FIFO and
is connected to a relatively slow system bus (APB) (with respect to the
SPI bus speed). In order to workaround the problems for as much as it's
possible, the memory operation execution procedure collects all the Tx
data into a single buffer and disables the local IRQs to speed the
write-then-optionally-read method up.
Note the provided memory operations are utilized by default only if
a glue driver hasn't provided a custom version of ones and this is not
a DW APB SSI controller with fixed automatic CS toggle functionality.
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20201007235511.4935-18-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Samsung S3C24xx and S3C64xx machine code cleanup for v5.10
Big cleanup for the Samsung S3C24xx and S3C64xx platforms, although it
also touches files shared with S5Pv210 and Exynos. This is mostly Arnd
Bergmann work which Krzysztof Kozlowski took over, rebased and polished.
The goal is to cleanup, merge and finally make the Samsung S3C24xx and
S3C64xx architectures multiplatform. The multiplatform did not happen
yet here - just cleaning up and merging into one arch/arm/mach-s3c
directory. However this is step forward for multiplatform or at least
to keep this code still maintainable.
This pulls also branch with changes for Samsung SoC sound drivers from
broonie/sound because the cleanups there were part of this series and
all further patches depend on them.
* tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (62 commits)
ARM: s3c: Avoid naming clash of S3C24xx and S3C64xx timer setup
ARM: s3c: Cleanup from old plat-samsung include
ARM: s3c: make headers local if possible
ARM: s3c: move into a common directory
ARM: s3c24xx: stop including mach/hardware.h from mach/io.h
cpufreq: s3c24xx: move low-level clk reg access into platform code
cpufreq: s3c2412: use global s3c2412_cpufreq_setrefresh
ARM: s3c: remove cpufreq header dependencies
cpufreq: s3c24xx: split out registers
fbdev: s3c2410fb: remove mach header dependency
ARM: s3c24xx: bast: avoid irq_desc array usage
ARM: s3c24xx: spi: avoid hardcoding fiq number in driver
ARM: s3c24xx: include mach/irqs.h where needed
ARM: s3c24xx: move s3cmci pinctrl handling into board files
ARM: s3c24xx: move iis pinctrl config into boards
ARM: s3c24xx: move spi fiq handler into platform
ARM: s3c: adc: move header to linux/soc/samsung
ARM: s3c24xx: move irqchip driver back into platform
ARM: s3c24xx: move regs-spi.h into spi driver
ARM: s3c64xx: remove mach/hardware.h
...
Link: https://lore.kernel.org/r/20200831154751.7551-1-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
CONFIG_OF_DYNAMIC and CONFIG_ACPI allow adding SPI devices at runtime
using a DeviceTree overlay or DSDT patch. CONFIG_SPI_SLAVE allows the
same via sysfs.
But there are no precautions to prevent adding a device below a
controller that's being removed. Such a device is unusable and may not
even be able to unbind cleanly as it becomes inaccessible once the
controller has been torn down. E.g. it is then impossible to quiesce
the device's interrupt.
of_spi_notify() and acpi_spi_notify() do hold a ref on the controller,
but otherwise run lockless against spi_unregister_controller().
Fix by holding the spi_add_lock in spi_unregister_controller() and
bailing out of spi_add_device() if the controller has been unregistered
concurrently.
Fixes: ce79d54ae4 ("spi/of: Add OF notifier handler")
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: stable@vger.kernel.org # v3.19+
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Octavian Purdila <octavian.purdila@intel.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Link: https://lore.kernel.org/r/a8c3205088a969dc8410eec1eba9aface60f36af.1596451035.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Optimezed mem*io operations are defined for LE platforms, use them.
The ARM and !ARCH_EBSA110 dependencies for COMPILE_TEST were added
only for the _memcpy_fromio()/_memcpy_toio() functions. Drop these
dependencies.
Tested unaligned accesses on both sama5d2 and sam9x60 QSPI controllers
using SPI NOR flashes, everything works ok. The following performance
improvement can be seen when running mtd_speedtest:
sama5d2_xplained (mx25l25635e)
- before:
mtd_speedtest: eraseblock write speed is 983 KiB/s
mtd_speedtest: eraseblock read speed is 6150 KiB/s
- after:
mtd_speedtest: eraseblock write speed is 1055 KiB/s
mtd_speedtest: eraseblock read speed is 20144 KiB/s
sam9x60ek (sst26vf064b)
- before:
mtd_speedtest: eraseblock write speed is 4770 KiB/s
mtd_speedtest: eraseblock read speed is 8062 KiB/s
- after:
mtd_speedtest: eraseblock write speed is 4524 KiB/s
mtd_speedtest: eraseblock read speed is 21186 KiB/s
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200716043139.565734-1-tudor.ambarus@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
<vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move
cadence-quadspi driver to spi-mem framework
Those patches were trying to accomplish too many things in a single set
of patches and need to split into smaller patches. This is reduced
version of above series.
Changes that are intended to make migration easy are split into separate
patches. Patches 1 to 3 drop features that cannot be supported under
spi-mem at the moment (backward compatibility is maintained).
Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
spi-mem and patch 7 moves the driver to drivers/spi folder.
I have tested both INDAC mode (used by non TI platforms like Altera
SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.
Patches to move move bindings over to
"Documentation/devicetree/bindings/spi/" directory and also conversion
of bindig doc to YAML will be posted separately. Support for Intel
platform would follow that.
Resend v3:
Rebased onto v5.7-c1
v3:
Split handling of probe deferral into separate patch (out of 5/6)
Split dropping of redundant WREN to separate patch (out of 5/6)
Fix a possible memleak due to lack of spi_master_put()
Parse all SPI slave nodes in cqspi_setup_flash()
Address misc comments from Tudor on v2
Rebase onto latest spi-nor/next
v2:
Rework patch 1/6 to keep "cdns,is-decoded-cs" property supported.
Ramuthevar Vadivel Murugan (2):
mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework
spi: Move cadence-quadspi driver to drivers/spi/
Vignesh Raghavendra (6):
mtd: spi-nor: cadence-quadspi: Make driver independent of flash
geometry
mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC mode
mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on
failure
mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire
reset lines
mtd: spi-nor: cadence-quadspi: Handle probe deferral while requesting
DMA channel
mtd: spi-nor: cadence-quadspi: Drop redundant WREN in erase path
drivers/mtd/spi-nor/controllers/Kconfig | 11 -
drivers/mtd/spi-nor/controllers/Makefile | 1 -
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
.../spi-cadence-quadspi.c} | 541 +++++++-----------
5 files changed, 222 insertions(+), 343 deletions(-)
rename drivers/{mtd/spi-nor/controllers/cadence-quadspi.c => spi/spi-cadence-quadspi.c} (74%)
base-commit: b3a9e3b962
--
2.26.2
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