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5719 Commits

Author SHA1 Message Date
Geert Uytterhoeven
d5ea70ead8 pinctrl: renesas: r8a77951: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cd59cc2e0f55f0dcede1356f73a9e69fe09bf5eb.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
8e8fb81292 pinctrl: renesas: r8a77950: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 473 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a1617d24af2b9b3224ce84c0ada535565009fdda.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
5b7dda3a49 pinctrl: renesas: r8a7792: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 257 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0f211d493a0cfbcd96d84a709d21bea51c7385ae.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
9794156d6b pinctrl: renesas: r8a7779: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 81 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ecc7377d2992694226dcf055bed0b617701a3d71.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
ade1ef9904 pinctrl: renesas: r8a77470: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 70 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c5183fcb3dd417d57ced0f60d091e2c7d37e1c8c.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
72ee7f9b6f pinctrl: renesas: r8a7740: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 230 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a18fb98a4eefe648a1b1c5b5913dbeee092674c4.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
9cad77c5c8 pinctrl: renesas: r8a73a4: Optimize fixed-width reserved fields 
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 126 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f835c2ff5bb07e541f6377b16f0a32c5aad2a47f.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
0479e084f7 pinctrl: renesas: sh7734: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 174 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3ab96d28494b8c5a2d427ba25f31a04ca0cc7305.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
cdc29f1088 pinctrl: renesas: r8a779f0: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 164 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c98e577996a71ae96145ee6da94aa18fd9ea85b9.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
599e16c147 pinctrl: renesas: r8a779a0: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 140 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/807b2a7e02be2fac50c280961a4841813ab13cd8.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
de3561ba2e pinctrl: renesas: r8a77995: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 246 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7098704f89bb702c28036c567d3222521ff60f86.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
f1bef7db75 pinctrl: renesas: r8a77990: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 40 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c032fce3fff6a6a63dc90f9ab8dfe1f4f3cf6ad6.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
10890813b2 pinctrl: renesas: r8a77980: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 168 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c81b26815dff2e191b8c415624a20aa3b4725d23.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
289acf3a99 pinctrl: renesas: r8a77970: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 164 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f2dda82454bb1b0c97f842de2c9fa68da05ef3e6.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
6088f726c9 pinctrl: renesas: r8a77965: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 148 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1cf52b1f93e8af593a60f65d8a848d1ebb24cac6.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
6c0c5abc07 pinctrl: renesas: r8a7796: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 148 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/433f5ddcc2dba7352825cba007b99b8e654d4c61.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
5e0857fd53 pinctrl: renesas: r8a77951: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 152 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35d0ff4881335889002718540101bcdb8e7f5b5a.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
18a5e80dba pinctrl: renesas: r8a77950: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 232 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1866c399e94408439a469c12dc53557b55a00f3a.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
6d261290d3 pinctrl: renesas: r8a7794: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 201 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2fa43bd38c5cf260e89ae1da38d1a217ab762589.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
cb53eb5455 pinctrl: renesas: r8a7792: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 784 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d39a52cf972a450ef5a0989ba7e448115a8147ba.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
d3fcaad605 pinctrl: renesas: r8a7791: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 349 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/972808be595fd742afc6b7fc89751ca4788d6f62.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
9bfb06a378 pinctrl: renesas: r8a7790: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 445 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/842d8060422a9b67dfac4af6d9325d0d99cf50dc.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
5ca9a715f5 pinctrl: renesas: r8a7779: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 197 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4b468118e0da681c860ed750976a990a0930dcba.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
0f1dd62cab pinctrl: renesas: r8a7778: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 142 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1af5225c81ac871a461f7d824619275e2e0ed8df.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
287f1ee38a pinctrl: renesas: r8a77470: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 114 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/bc8f9647bbf677ac67cbdb34cf0c8fbaf62fb7fc.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
ead4017fcd pinctrl: renesas: emev2: Use shorthands for reserved fields 
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 769 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/616afe67d3b4d2cbf5f43876f9aa7b258862ceaa.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
44778aec5e pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved 
The PULMD bits and the SEC bit in the PORTCR register descriptions on
SH/R-Mobile SoCs are either unused or unsupported.  Describe them as
reserved bits using a negative field width value, and drop the
corresponding dummy enum IDs.

This reduces kernel size by 2832 (R-Mobile APE6), 2544 (R-Mobile A1),
and/or 3228 (SH-Mobile AG5) bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1b123d8f04c2314d5a7a87004971868ba2176499.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
6210905586 pinctrl: renesas: Add shorthand for reserved register fields 
Currently, reserved register fields must be fully described using dummy
enum IDs (zeroes), one for each possible state (2^bits states).

Add support for describing reserved fields using negative field width
values as shorthands, thus removing the need for dummy values.  Apart
from the obvious size reduction due to the removal of the dummy values,
this will also enable merging adjacent reserved fields into a single
field, reducing the number of fields to describe, and thus kernel size.

Update the checker accordingly.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cad7c92ef039d9a4d039807efc15886a7aa862be.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Geert Uytterhoeven
7fefb7c059 pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs 
All fields in the IPSR registers on RZ/G1C have the same width, but the
driver describes them using the PINMUX_CFG_REG_VAR() macro, which
is intended for fields with different widths.  Convert the description
to use the PINMUX_CFG_REG() macro for fixed-width fields instead.

This reduces kernel size by 162 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f6f26a0dfd16050ead83daf2b9fabeb8b26821a6.1649865241.git.geert+renesas@glider.be
 2022-05-05 12:02:25 +02:00
Andy Shevchenko
f4f1739a09 pinctrl: nomadik: Setup parent device and get rid of unnecessary of_node assignment 
Some of the drivers do not set parent device. This may lead to obstacles
during debugging or understanding the device relations from the Linux
point of view. Assign parent device for GPIO chips created by these
drivers.

While at it, let GPIO library to assign of_node from the parent device.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220503151310.58762-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-05 00:08:06 +02:00
Fabien Dessenne
3389b09878 pinctrl: stm32: prevent the use of the secure protected pins 
The hardware denies any access from the Linux non-secure world to the
secure-protected pins. Hence, prevent any driver to request such a pin.

Mark the secure-protected GPIO lines as invalid (.init_valid_mask) and
prevent the pinmux request / pinconf setting operations.
Identify the secure pins with "NO ACCESS" in the pinconf sysfs.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Link: https://lore.kernel.org/r/20220502153114.283618-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-05 00:04:04 +02:00
Fabien Dessenne
3296c473d9 pinctrl: stm32: improve debugfs information of pinconf-pins entry 
Print the name of the selected alternate function in addition to its
number. Ex:
   "pin 135 (PI7): alternate 10 (SAI2_FS_A) - ..."

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20220502152524.283374-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-05 00:02:48 +02:00
Hector Martin
b983d423ce pinctrl: apple: Make it work as a module 
We need MODULE_DEVICE_TABLE for module autoloading to work.

Signed-off-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20220502092335.30670-1-marcan@marcan.st
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-05 00:00:37 +02:00
Krzysztof Kozlowski
e804944dcc pinctrl: nuvoton: Fix irq_of_parse_and_map() return value 
The irq_of_parse_and_map() returns 0 on failure, not a negative ERRNO.

Fixes: 3b588e43ee ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220423094142.33013-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-04 23:48:40 +02:00
Krzysztof Kozlowski
a9387099d8 pinctrl: tegra: tegra194: drop unused pin groups 
The sdmmc1_hv_trim_pins, sdmmc3_hv_trim_pins and sys_reset_n_pins are
not defined as pin groups:

  drivers/pinctrl/tegra/pinctrl-tegra194.c:1119:27: error: ‘sdmmc3_hv_trim_pins’ defined but not used [-Werror=unused-const-variable=]
   1119 | static const unsigned int sdmmc3_hv_trim_pins[] = {

Proper fix would be to define them, but this requires knowledge from
datasheet.  Removal should not cause any harm and at least it silences
the warnings.

Fixes: 613c082608 ("pinctrl: tegra: Add pinmux support for Tegra194")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220429061332.25135-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-04 23:40:05 +02:00
Linus Walleij
a091208308 Merge tag 'intel-gpio-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel 
intel-gpio for v5.19-1

* Introduce helpers to iterate over GPIO chip nodes and covert some drivers

The following is an automated git shortlog grouped by driver:

gpiolib:
 -  Introduce a helper to get first GPIO controller node
 -  Introduce gpiochip_node_count() helper
 -  Introduce for_each_gpiochip_node() loop helper

pinctrl:
 -  meson: Replace custom code by gpiochip_node_count() call
 -  meson: Enable COMPILE_TEST
 -  meson: Rename REG_* to MESON_REG_*
 -  armada-37xx: Reuse GPIO fwnode in armada_37xx_irqchip_register()
 -  armada-37xx: Switch to use fwnode instead of of_node
 -  samsung: Switch to use for_each_gpiochip_node() helper
 -  samsung: Drop redundant node parameter in samsung_banks_of_node_get()
 -  npcm7xx: Switch to use for_each_gpiochip_node() helper
 -  renesas: rza1: Switch to use for_each_gpiochip_node() helper
 -  renesas: rza1: Replace custom code by gpiochip_node_count() call
 -  stm32: Switch to use for_each_gpiochip_node() helper
 -  stm32: Replace custom code by gpiochip_node_count() call
 2022-05-04 23:15:21 +02:00
Arnd Bergmann
2391e0d7bd Merge tag 'aspeed-v5.18-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/fixes 
ASPEED device tree fixes for v5.18

 - Quad SPI device tree corrections

 - Reinstate GFX node that was removed

 - romed8hm3 machine fixes

* tag 'aspeed-v5.18-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc:
  ARM: dts: aspeed: Add video engine to g6
  ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
  ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
  ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group
  ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi
  dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
  pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
  dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
  pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
  ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi

Link: https://lore.kernel.org/r/CACPK8XdhLfafOfqvR0r7p6V6AhtNXD4uZGaz7Y+Y4P-rc9p0tQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-05-03 16:06:29 +02:00
Yang Yingliang
2f661477c2 pinctrl: renesas: rzn1: Fix possible null-ptr-deref in sh_pfc_map_resources() 
It will cause null-ptr-deref when using 'res', if platform_get_resource()
returns NULL, so move using 'res' after devm_ioremap_resource() that
will check it to avoid null-ptr-deref.
And use devm_platform_get_and_ioremap_resource() to simplify code.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220429082637.1308182-2-yangyingliang@huawei.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-03 10:03:15 +02:00
Yang Yingliang
5376e3d904 pinctrl: renesas: core: Fix possible null-ptr-deref in sh_pfc_map_resources() 
It will cause null-ptr-deref when using 'res', if platform_get_resource()
returns NULL, so move using 'res' after devm_ioremap_resource() that
will check it to avoid null-ptr-deref.
And use devm_platform_get_and_ioremap_resource() to simplify code.

Fixes: c7977ec4a3 ("pinctrl: sh-pfc: Convert to platform_get_*()")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20220429082637.1308182-1-yangyingliang@huawei.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-03 10:03:12 +02:00
Geert Uytterhoeven
8bdd369dba pinctrl: renesas: r8a779f0: Fix GPIO function on I2C-capable pins 
Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral
Function Select Register (GPSRn) on R-Car S4-8 is not always sufficient
to configure a pin for GPIO.  For I2C-capable pins, the I2C function
must also be explicitly disabled in the corresponding Module Select
Register (MODSELn).

Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array
by temporarily overriding the GP_1_j_FN function enum to expand to two
enums: the original GP_1_j_FN enum to configure the GPSR register bits,
and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register
bits.

Fixes: 030ac6d7ee ("pinctrl: renesas: Initial R8A779F0 PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c12c60ec1058140a37f03650043ab73f730f104f.1650610471.git.geert+renesas@glider.be
 2022-05-03 09:58:25 +02:00
Geert Uytterhoeven
4288caed9a pinctrl: renesas: r8a779a0: Fix GPIO function on I2C-capable pins 
Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral
Function Select Register (GPSRn) on R-Car V3U is not always sufficient
to configure a pin for GPIO.  For I2C-capable pins, the I2C function
must also be explicitly disabled in the corresponding Module Select
Register (MODSELn).

Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array
by temporarily overriding the GP_2_j_FN function enum to expand to two
enums: the original GP_2_j_FN enum to configure the GSPR register bits,
and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register
bits.

Fixes: 741a7370fc ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4611e29e7b105513883084c1d6dc39c3ac8b525c.1650610471.git.geert+renesas@glider.be
 2022-05-03 09:57:35 +02:00
Bartosz Golaszewski
c85b2f15f5 Merge tag 'intel-gpio-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into gpio/for-next 
intel-gpio for v5.19-1

* Introduce helpers to iterate over GPIO chip nodes and covert some drivers

gpiolib:
 -  Introduce a helper to get first GPIO controller node
 -  Introduce gpiochip_node_count() helper
 -  Introduce for_each_gpiochip_node() loop helper

pinctrl:
 -  meson: Replace custom code by gpiochip_node_count() call
 -  meson: Enable COMPILE_TEST
 -  meson: Rename REG_* to MESON_REG_*
 -  armada-37xx: Reuse GPIO fwnode in armada_37xx_irqchip_register()
 -  armada-37xx: Switch to use fwnode instead of of_node
 -  samsung: Switch to use for_each_gpiochip_node() helper
 -  samsung: Drop redundant node parameter in samsung_banks_of_node_get()
 -  npcm7xx: Switch to use for_each_gpiochip_node() helper
 -  renesas: rza1: Switch to use for_each_gpiochip_node() helper
 -  renesas: rza1: Replace custom code by gpiochip_node_count() call
 -  stm32: Switch to use for_each_gpiochip_node() helper
 -  stm32: Replace custom code by gpiochip_node_count() call
 2022-05-02 11:44:02 +02:00
Fabien Dessenne
c954531bc5 pinctrl: stm32: improve bank clocks management 
Instead of enabling/disabling the clock at each IO configuration update,
just keep the clock enabled from the probe.
This makes things simpler and more efficient (e.g. the time required to
toggle an output IO is drastically decreased) without significantly
increasing the power consumption.

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220422143608.226580-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-01 23:25:58 +02:00
Linus Walleij
f930b69a89 Merge tag 'v5.18-rc5' into devel 
Merge in Linux 5.18-rc5 since new code to the STM32 driver
depend in a non-trivial way on the fixes merged in -rc5.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-01 23:25:10 +02:00
Mattijs Korpershoek
f680058f40 pinctrl: mediatek: mt8365: fix IES control pins 
IES26 (BIT 16 of IES1_CFG_ADDR) controls the following pads:

- PAD_I2S_DATA_IN (GPIO114)
- PAD_I2S_LRCK (GPIO115)
- PAD_I2S_BCK (GPIO116)

The pinctrl table is wrong since it lists pins 114 to 112.

Update the table with the correct values.

Fixes: e94d8b6fb8 ("pinctrl: mediatek: add support for mt8365 SoC")
Reported-by: Youngmin Han <Youngmin.Han@geappliances.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20220426125714.298907-1-mkorpershoek@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-01 23:24:18 +02:00
Horatiu Vultur
d3683eeb9d pinctrl: ocelot: Fix for lan966x alt mode 
For lan966x, the GPIO 35 has the wrong function for alternate mode 2.
The mode is not none but is PTP sync.

Fixes: 531d6ab365 ("pinctrl: ocelot: Extend support for lan966x")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Link: https://lore.kernel.org/r/20220413192918.3777234-1-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-05-01 23:24:18 +02:00
Andy Shevchenko
608a0b46bc Merge branch 'irq/gpio-immutable' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into intel/pinctrl 
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 2022-04-29 13:02:08 +03:00
Jianqun Xu
fdc33eba11 pinctrl/rockchip: add rk3588 support 
Add pinctrl support for RK3588.

[merged in downstream fixes, simplified register lookup logic for better
maintanence at the cost of a bit more static const memory and fixed some
incorrect registers]

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220422170920.401914-14-sebastian.reichel@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-04-29 00:55:02 +02:00
Sebastian Reichel
42573ab3b9 pinctrl/rockchip: add error handling for pull/drive register getters 
Add error handling for the pull and driver register getters in preparation
for RK3588 support.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Heiko Stübner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220422170920.401914-13-sebastian.reichel@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-04-29 00:54:15 +02:00
Krzysztof Kozlowski
71bc7cf3be pinctrl: mvebu: Fix irq_of_parse_and_map() return value 
The irq_of_parse_and_map() returns 0 on failure, not a negative ERRNO.

Fixes: 2f22760539 ("pinctrl: armada-37xx: Add irqchip support")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220422105339.78810-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-04-29 00:49:11 +02:00