The clock register definitions are now used (almost) exclusively in the
clk driver, and that relies on no other mach/*.h header files any more.
Remove the dependency on mach/pxa*-regs.h by addressing the registers
as offsets from a void __iomem * pointer, which is either passed from
a board file, or (for the moment) ioremapped at boot time from a hardcoded
address in case of DT (this should be moved into the DT of course).
Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The driver needs some low-level register access for setting
the core and bus frequencies. These registers are owned
by the clk driver, so move the low-level access into that
driver with a slightly higher-level interface and avoid
any machine header file dependencies.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The RTC section of the H616 manual mentions in a half-sentence the
existence of a clock "32K divided by PLL_PERI(2X)". This is used as
one of the possible inputs for the mux that selects the clock for the
32 KHz fanout pad. On the H616 this is routed to pin PG10, and some
boards use that clock output to compensate for a missing 32KHz crystal.
On the OrangePi Zero2 this is for instance connected to the LPO pin of
the WiFi/BT chip.
The new RTC clock binding requires this clock to be named as one input
clock, so we need to expose this to the DT. In contrast to the D1 SoC
there does not seem to be a gate for this clock, so just use a fixed
divider clock, using a newly assigned clock number.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220428230933.15262-3-andre.przywara@arm.com
The H6 and H616 feature an (undocumented) bus clock gate for accessing
the RTC registers. This seems to be enabled at reset (or by the BootROM),
so we got away without it so far, but exists regardless.
Since the new RTC clock binding for the H616 requires this "bus" clock
to be specified in the DT, add this to R_CCU clock driver and expose it
on the DT side with a new number.
We do this for both the H6 and H616, but mark it as IGNORE_UNUSED, as we
cannot reference it in any H6 DTs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220428230933.15262-2-andre.przywara@arm.com
For some DFLL functions, the kerneldoc comments don't match the function
prototype. Fix them up to avoid some warnings at build time.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Just like in case of other SoCs change SDCC1/SDCC2 ops
to floor to avoid overclocking controller.
This commit only sets SDCC1/SDCC2 which are used for EMMC/SDCARD.
Leave SDCC3 because on this platform it's mostly used for WIFI/BT chips,
like on Sony Loire familly devices.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426073048.11509-2-a39.skl@gmail.com
Replace the .round_rate() callback with .determine_rate() which can
consider max_rate imposed by clk_set_max_rate() while rounding the clock
rate.
Note that if the .determine_rate() callback is defined it will be called
instead of the .round_rate() callback when calling clk_round_rate(). By
using .determine_rate(), the maximum rate returned when calling
clk_round_rate() is now limited by the current max_rate.
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
[jonathanh@nvidia.com: checkpatch fixes and commit message update]
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Current clock initialization causes intermediate registering of orphan
clocks (i.e. a clock without a parent registered). CCF keeps track of
orphan clocks and any time a new clock is registered, it will loop
through the list of orphan and queries if the parent is now available.
This operation triggers one or more clock operations, which are IPCs
with BPMP-FW. Hence, due to the order in which the clocks appear
currently, this causes > 5000 IPC messages to be sent to BPMP-FW during
clock initialization.
Optimize the clock probing by registering clocks hierarchically from
root clock towards leafs.
Signed-off-by: Timo Alho <talho@nvidia.com>
[jonathanh@nvidia.com: checkpatch fixes]
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Commit 4782c0a5dd ("clk: tegra: Don't deassert reset on enabling
clocks") removed deassertion of reset lines when enabling peripheral
clocks. This breaks the initialization of the DFLL driver which relied
on this behaviour.
Fix this problem by adding explicit deassert/assert requests to the
driver. Tested on Google Pixel C.
Cc: stable@vger.kernel.org
Fixes: 4782c0a5dd ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Whenever pclk_vo is enabled hclk_vo must be enabled as well. This is
described in the Reference Manual as:
| 2.8.6 NIU Clock gating reliance
|
| A part of niu clocks have a dependence on another niu clock in order to
| sharing the internal bus. When these clocks are in use, another niu
| clock must be opened, and cannot be gated. These clocks and the special
| clock on which they are relied are as following:
|
| Clocks which have dependency The clock which can not be gated
| -----------------------------------------------------------------
| ...
| pclk_vo_niu, hclk_vo_s_niu hclk_vo_niu
| ...
The clock framework doesn't offer a way to enable clock B whenever clock A is
enabled, at least not when B is not an ancestor of A. Workaround this by
marking hclk_vo as critical so it is never disabled. This is suboptimal in
terms of power consumption, but a stop gap solution until the clock framework
has a way to deal with this.
We have this clock tree:
| aclk_vo 2 2 0 300000000 0 0 50000 Y
| aclk_hdcp 0 0 0 300000000 0 0 50000 N
| pclk_vo 2 3 0 75000000 0 0 50000 Y
| pclk_edp_ctrl 0 0 0 75000000 0 0 50000 N
| pclk_dsitx_1 0 0 0 75000000 0 0 50000 N
| pclk_dsitx_0 1 2 0 75000000 0 0 50000 Y
| pclk_hdmi_host 1 2 0 75000000 0 0 50000 Y
| pclk_hdcp 0 0 0 75000000 0 0 50000 N
| hclk_vo 2 5 0 150000000 0 0 50000 Y
| hclk_hdcp 0 0 0 150000000 0 0 50000 N
| hclk_vop 0 2 0 150000000 0 0 50000 N
Without this patch the edp, dsitx, hdmi and hdcp driver would enable their
clocks which then enables pclk_vo, but hclk_vo stays disabled and register
accesses just hang. hclk_vo is enabled by the VOP2 driver, so reproducibility
of this issue depends on the probe order.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20220422072841.2206452-2-s.hauer@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
If the device is already in a runtime PM enabled state
pm_runtime_get_sync() will return 1.
Also, we need to call pm_runtime_put_noidle() when pm_runtime_get_sync()
fails, so use pm_runtime_resume_and_get() instead. this function
will handle this.
Fixes: 78edeb0803 ("clk: imx: scu: add runtime pm support")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220425011117.25093-1-linmq006@gmail.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
