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11254 Commits

Author SHA1 Message Date
Jack Xiao
de33a32968 drm/amdgpu: use the whole doorbell space for mes 
Use the whole doorbell space for mes. Each queue in one process occupies
one doorbell slot to ring the queue submitting.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:04:01 -04:00
Jack Xiao
564434020a drm/amdgpu/gmc10: skip emitting pasid mapping packet 
For MES FW manages IH_VMID_x_LUT updating, skip emitting pasid
mapping packet.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:58 -04:00
Jack Xiao
115efa440f drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2 
For MES queue VM flush, use INVALIDATE_TLBS to invalidate TLBs.
This packet can let CP firmware to determine the current vmid
and inv eng to invalidate.

v2: unify invalidate_tlbs functions

Cc: Le Ma <le.ma@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:54 -04:00
Jack Xiao
1f0f303c85 drm/amdgpu/gfx10: inherit vmid from mqd 
For MES manages vmid assignment, let vmid inherit from mqd instead of
ib packet setting.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:47 -04:00
Jack Xiao
11f39576ac drm/amdgpu/gfx10: associate mes queue id with fence v2 
Associate mes queue id with fence, so that EOP trap handler can look up
which queue has issued the fence.

v2: move mes queue flag to amdgpu_mes_ctx.h

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:45 -04:00
Jack Xiao
34ec3c2e0e drm/amdgpu/gfx10: use per ctx CSA for de metadata 
As MES requires per context preemption, use per context CSA address
for DE metadata to correctly enable context MCBP preemption.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:43 -04:00
Jack Xiao
75df9e88c5 drm/amdgpu/gfx10: use per ctx CSA for ce metadata 
As MES requires per context preemption, use per context CSA address
for CE metadata to correctly enable context MCBP preemption.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:40 -04:00
Jack Xiao
c755f68095 drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2 
Refine the existing gfx/compute mqd functions, and add them
to engine mqd layer.

v2: rebase fix.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:35 -04:00
Jack Xiao
ae9fd76fd8 drm/amdgpu: assign the cpu/gpu address of fence from ring 
assign the cpu/gpu address of fence for the normal or mes ring
from ring structure.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:31 -04:00
Jack Xiao
502b6cef8f drm/amdgpu: initialize/finalize the ring for mes queue 
Iniailize/finalize the ring for mes queue which submits the command
stream to the mes-managed hardware queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:29 -04:00
Jack Xiao
3748424ba9 drm/amdgpu: use ring structure to access rptr/wptr v2 
Use ring structure to access the cpu/gpu address of rptr/wptr.

v2: merge gfx10/sdma5/sdma5.2 patches

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:27 -04:00
Jack Xiao
d74c5b06e6 drm/amdgpu: define ring structure to access rptr/wptr/fence 
Define ring structure to access the cpu/gpu address of rptr/wptr/fence
instead of dynamic calculation.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:23 -04:00
Jack Xiao
c6abbcbc76 drm/amdgpu: add mes ctx data in amdgpu_ring 
Add mes context data structure in amdgpu_ring.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:20 -04:00
Jack Xiao
2bc956ef54 drm/amdgpu: add the per-context meta data v3 
The per-context meta data is a per-context data structure associated
with a mes-managed hardware ring, which includes MCBP CSA, ring buffer
and etc.

v2: fix typo
v3: a. use structure instead of typedef
    b. move amdgpu_mes_ctx_get_offs_* to amdgpu_ring.h
    c. use __aligned to make alignement

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:17 -04:00
Jack Xiao
80af9daa62 drm/amdgpu: add helper function to initialize mqd from ring v4 
Add the helper function to initialize mqd from ring configuration.

v2: use if/else pair instead of ?/: pair
v3: use simpler way to judge hqd_active
v4: fix parameters to amdgpu_gfx_is_high_priority_compute_queue

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:14 -04:00
Jack Xiao
5405a52627 drm/amdgpu: define MQD abstract layer for hw ip 
Define MQD abstract layer for hw ip, for the passing
mqd configuration not only from ring but more sources,
like user queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:11 -04:00
Likun Gao
d142f56e4f drm/amdgpu: add imu fw structure 
Add IMU firmware structure.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:07 -04:00
Likun Gao
89466f49b2 drm/amdgpu: add rlc TOC header file for soc21 (v2) 
Add RLC autoload TOC header file for soc21 ASIC.

v2: squash in updates

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:03:04 -04:00
Likun Gao
550bb28e64 drm/amdgpu: support rlc v2_3 ucode struct 
Add support for rlc v2_3 to support RLCV and RLCP fw load.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:38 -04:00
Likun Gao
641f053e3e drm/amdgpu: add gfx firmware header v2_0 
We need define new firmware header to support
CP RS64 fw.

Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:36 -04:00
Hawking Zhang
6c982cf878 drm/amdgpu: add gfx11 clearstate header 
Add gfx11 clearstate register arrays

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:20 -04:00
Likun Gao
7d33614285 drm/amdgpu/discovery: Set GC family for GC 11.0 IP 
Set GC family for GC 11.0 IPs.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:02:14 -04:00
Alice Wong
ab0cd4a9ae drm/amdgpu/ucode: Remove firmware load type check in amdgpu_ucode_free_bo 
When psp_hw_init failed, it will set the load_type to AMDGPU_FW_LOAD_DIRECT.
During amdgpu_device_ip_fini, amdgpu_ucode_free_bo checks that load_type is
AMDGPU_FW_LOAD_DIRECT and skips deallocating fw_buf causing memory leak.
Remove load_type check in amdgpu_ucode_free_bo.

Signed-off-by: Alice Wong <shiwei.wong@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:01:53 -04:00
Likun Gao
40c487409a drm/amdgpu/discovery: Enable SMU for SMU 13.0.0 
Enable SMU on SMU IP version 13.0.0

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:59:01 -04:00
Evan Quan
a6dec86840 drm/amdgpu/soc21: enable ATHUB and MMHUB PG 
Enable ATHUB and MMHUB powergating.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:58:59 -04:00
Evan Quan
b37c41f2cb drm/amdgpu: enable pptable ucode loading 
With SCPM enabled, pptable cannot be uploaded to SMU directly.
The transferring has to be via PSP.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:58:00 -04:00
Hawking Zhang
f0b0a1b806 drm/amdgpu: query core refclk from bios for smu v13 
The smu_info structrue for smu v13 is changed that
core_refclk in v31 strucuture is not correct for
smu v13_0_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:35 -04:00
Likun Gao
0984d38441 drm/amdgpu/discovery: add GMC 11.0 Support 
Enable GMC 11.0 on asics where it is present.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:29 -04:00
Tianci.Yin
1c2014da77 drm/amdgpu: add gmc v11_0 ip block (v3) 
Add support for GPU memory controller v11.

v1: Add support for gmc v11.0
    Add gmc 11 block (Tianci)
v2: drop unused amdgpu_bo_late_init (Hawking)
v3: squash in various fix

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:26 -04:00
Jack Xiao
d7dab4fc44 drm/amdgpu: save the setting of VM_CONTEXT_CNTL 
MES firmware needs the setting of VM_CONTEXT_CNTL to perform
vmid switch. Save the initial setting when hub initializing.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:22 -04:00
Tianci.Yin
98a0f8687e drm/amdgpu: add mmhub v3_0 ip block 
Add support for mmhub v3.0

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:18 -04:00
Tianci.Yin
2279b4e596 drm/amdgpu: add gfxhub v3_0 ip block 
Add support for gfxhub v3.0

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:13 -04:00
Tianci.Yin
ae460cd566 drm/amdgpu: add athub v3_0 ip block 
Add support for athub v3.0

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:10 -04:00
Likun Gao
55a800da49 drm/amdgpu/discovery: Enable PSP for PSP 13.0.0 
Enable PSP on PSP IP version 13.0.0

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:57:00 -04:00
Likun Gao
7f318f4e30 drm/amdgpu: add tracking for the enablement of SCPM 
Add parmeter to shows whether SCPM feature is enabled or not, and
whether is valid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:56:51 -04:00
Likun Gao
a6b6d38ed8 drm/amdgpu: rework psp firmware name 
Use the new helper for deriving the fw name from
the IP version.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:30 -04:00
Likun Gao
911a75043f drm/amdgpu: support psp v13_0_0 microcode init 
Support psp v13_0_0 microcode init.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:27 -04:00
Likun Gao
e995e2ecdf drm/amdgpu: add support for spl fw load on psp v13 
Support for spl firmware load on psp v13.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:23 -04:00
Likun Gao
47a2038554 drm/amdgpu: extend PSP GFX FW type 
Extend PSP GFX FW type to support IMU, LSDMA, SDMA v6, RS64 MES related
fw load.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:18 -04:00
Hawking Zhang
5fea10d5a9 drm/amdgpu: support print psp v2_0 hdr debug information 
print out psp firmware v2_0 hdr information for debugging
purpose

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:13 -04:00
Alice Wong
e2c34219d1 drm/amdgpu/psp: deallocate memory when psp_load_fw failed 
psp_load_fw failure would cause memory leak for psp tmr and psp ring
because psp_hw_init is not called as psp block is not fully initialized.
Clean up psp tmr and psp ring when psp_load_fw fail by calling
psp_free_shared_bufs and psp_ring_destroy.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alice Wong <shiwei.wong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:07 -04:00
Alex Deucher
da40bf8f93 drm/amdgpu/psp: move shared buffer frees into single function 
So we can properly clean up if any of the TAs or TMR fails
to properly initialize or terminate.  This avoids any
memory leaks in the error case.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:05 -04:00
Alex Deucher
fb4f4f4256 drm/amdgpu/psp: fix memory leak in terminate functions 
Make sure we free the memory even if the unload fails.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:55:02 -04:00
Alex Deucher
f03d97b0bd drm/amdgpu/psp: drop load/unload/init_shared_buf wrappers 
Just call the load/unload/init_shared_buf functions
directly.  Makes the code easier to follow.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:54:58 -04:00
Hawking Zhang
996ea8591b drm/amdgpu: init smuio v13_0_6 callbacks 
initialize smuio callback for soc21

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:54:46 -04:00
Alex Deucher
b95b539168 drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init 
Memory allocations should be done in sw_init.  hw_init should
just be hardware programming needed to initialize the IP block.
This is how most other IP blocks work.  Move the GPU memory
allocations from psp hw_init to psp sw_init and move the memory
free to sw_fini.  This also fixes a potential GPU memory leak
if psp hw_init fails.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:54:41 -04:00
Hawking Zhang
e6e405e048 drm/amdgpu: add smuio v13_0_6 support 
add smuio v13_0_6 callbacks to support read
rom image

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:54:38 -04:00
Likun Gao
1761e5efab drm/amdgpu/discovery: add HDP v6 
Enable HDP v6 on asics where it is present.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:54:01 -04:00
Likun Gao
563fcfbf31 drm/amdgpu: add hdp version 6 functions 
Unify hdp related function into hdp structure for hdp version 6.
V2: Remove hdp invalidate function as hdp v6 doesn't have read cache.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:53:58 -04:00
Philip Yang
068421b173 drm/amdgpu: Free user pages if kvmalloc_array fails 
To cleanup the BOs of bo_list which have got user pages.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:53:40 -04:00