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perf/x86/rapl: Add msr mask support

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In some cases, when probing a perf MSR, we're probing certain bits of the
MSR instead of the whole register, thus only these bits should be checked.

For example, for RAPL ENERGY_STATUS MSR, only the lower 32 bits represents
the energy counter, and the higher 32bits are reserved.

Introduce a new mask field in struct perf_msr to allow probing certain
bits of a MSR.

This change is transparent to the current perf_msr_probe() users.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20210204161816.12649-1-rui.zhang@intel.com
This commit is contained in:
Zhang Rui 2021-02-05 00:18:14 +08:00 committed by Peter Zijlstra
parent b3c3361fe3
commit ffb20c2e52
2 changed files with 10 additions and 4 deletions
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7
arch/x86/events/probe.c
View File

@ -28,6 +28,7 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
for (bit = 0; bit < cnt; bit++) {
if (!msr[bit].no_check) {
struct attribute_group *grp = msr[bit].grp;
u64 mask;
/* skip entry with no group */
if (!grp)
@ -44,8 +45,12 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
/* Virt sucks; you cannot tell if a R/O MSR is present :/ */
if (rdmsrl_safe(msr[bit].msr, &val))
continue;
mask = msr[bit].mask;
if (!mask)
mask = ~0ULL;
/* Disable zero counters if requested. */
if (!zero && !val)
if (!zero && !(val & mask))
continue;
grp->is_visible = NULL;

7
arch/x86/events/probe.h
View File

@ -4,10 +4,11 @@
#include <linux/sysfs.h>
struct perf_msr {
u64 msr;
struct attribute_group *grp;
u64 msr;
struct attribute_group *grp;
bool (*test)(int idx, void *data);
bool no_check;
bool no_check;
u64 mask;
};
unsigned long